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ECE520 - Lecture 2 Slide: 1 University of New Mexico

Office: ECE Bldg. 230B
Office hours: Tuesday 2:00-3:00PM or by appointment
E-mail: payman@ece.unm.edu
Payman Zarkesh-Ha
ECE520 VLSI Design
Lecture 2: Basic MOS Physics
ECE520 - Lecture 2 Slide: 2 University of New Mexico
Review of Last Lecture
Semiconductor technology trend and Moors law
Benefits of transistor scaling:
More functionality in the same foot print
Faster device
Devices with less switching energy
Less cost/function
Challenges of transistor scaling:
Device size reaching quantum level
Power dissipation and heat removal concerns
Interconnect worsen by scaling
Manufacturing yield issues
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ECE520 - Lecture 2 Slide: 3 University of New Mexico
Todays Lecture
Overview of Diode Physics
BASIC MOS Physics:
Understanding of device operation
Basic device equations for long channel MOSFET
Long channel MOS models for manual analysis
ECE520 - Lecture 2 Slide: 4 University of New Mexico
Reading Assignment
Today we will review Chapter 3 (MOS Physics)
Skim through Diodes but focus on Section 3.2.3 (diode transient behavior)
Study Section 3.3 (MOS transistor) thoroughly
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ECE520 - Lecture 2 Slide: 5 University of New Mexico
The Diode
n
p
p
n
B A
SiO
2
Al
A
B
Al
A
B
Cross-section of pn -junction in an IC process
One-dimensional
representation diode symbol
ECE520 - Lecture 2 Slide: 6 University of New Mexico
Depletion Region
hole diffusion
electron diffusion
p n
hole drift
electron drift
Charge
Density
Distance
x +
-
Electrical
x
Field
x
Potential
V

W
2
-W
1

0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostatic
potential.
Built-in potential
4
ECE520 - Lecture 2 Slide: 7 University of New Mexico
Forward Bias Diode
x
p
n0
n
p0
-W
1
W
2
0
p
n
(
W
2
)
n-region
p-region
L
p
diffusion
Typically avoided in Digital ICs
ECE520 - Lecture 2 Slide: 8 University of New Mexico
Reverse Bias Diode
x
p
n0
n
p0
-W
1
W
2
0
n-region
p-region
diffusion
The Dominant Operation Mode
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ECE520 - Lecture 2 Slide: 9 University of New Mexico
Diode IV Curve
ECE520 - Lecture 2 Slide: 10 University of New Mexico
Junction Capacitance
|
|
.
|

\
|
= |
2
i
D A
0
n
N N
Ln
q
KT
1
0
D A
D A si
D 0 j
N N
N N
2
q
A C

|
|
|
.
|

\
|
+
c
=
Built-in potential
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ECE520 - Lecture 2 Slide: 11 University of New Mexico
Diffusion Capacitance
q
KT
T
= |
Thermal Potential
ECE520 - Lecture 2 Slide: 12 University of New Mexico
What is a Transistor?
V
GS

>
V
T
R
on
S
D
A Switch!
|V
GS
|
An MOS Transistor
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ECE520 - Lecture 2 Slide: 13 University of New Mexico
MOSFET Top & Cross Section View
Metal Oxide Semiconductor Field Effect Transistor
ECE520 - Lecture 2 Slide: 14 University of New Mexico
NMOS Device Cross-Section
Source Drain
Gate
Bulk
I
DS
is Defined as from Drain to Source Current
Majority carriers are electrons
NMOS device conducts when gate-to-source voltage is positive
I
DS
is as a function of:
Channel width (W)
Inverse of channel length (1/L)
Gate-to-source potential (V
GS
)
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ECE520 - Lecture 2 Slide: 15 University of New Mexico
PMOS Device Cross-Section
Source Drain
Gate
Bulk
Complement of NMOS
Built inside an N-well implant in substrate
Majority carriers are holes, not electrons
Conducts when gate-source voltage is negative
ECE520 - Lecture 2 Slide: 16 University of New Mexico
Device Operation: Cutoff
Cutoff region (V
GS
= 0 )
The Source to Drain connection looks like two back to back
series connected diode
Therefore ideally I
DS
= 0
1
st
order approximation only
V
GS
=0
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ECE520 - Lecture 2 Slide: 17 University of New Mexico
Polysilicon gate forms a conductive top plate of a
capacitor
Gate oxide forms the dielectric of a parallel plate capacitor
P-doped substrate forms the conductive bottom plate of a capacitor
Gate Oxide Capacitance
ECE520 - Lecture 2 Slide: 18 University of New Mexico
Device Operation: Depletion
As gate potential increases
Positive majority carriers (holes) in the substrate repelled
from the surface (depleting the material of carriers)
A depletion region is formed under the surface of the gate
This depletion region is formed as potential at the silicon
surface underneath the gate reaches
F
|
|
.
|

\
|
=
i
A
F
n
N
Ln
q
KT
|
small V
GS
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ECE520 - Lecture 2 Slide: 19 University of New Mexico
Device Operation: Inversion
As the surface potential beneath the gate increases
beyond
F
Electrons from heavily doped source and drain are attracted to
the gate and move into the channel
When the surface potential reaches 2
F
the charge density of
electrons in the channel equals the original doping density of the
P-substrate
At this time the channel is inverted
Therefore, a conductive path is formed between source and drain
Large V
GS
ECE520 - Lecture 2 Slide: 20 University of New Mexico
Device Operation: Inversion
Inversion region is simply a resistor
We need an applied V
DS
to get current flow
When drain voltage is applied the depletion region
grows at the drain junction
Large V
GS
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ECE520 - Lecture 2 Slide: 21 University of New Mexico
MOSFET Band Diagram
ECE520 - Lecture 2 Slide: 22 University of New Mexico
MOSFET Threshold Voltage
V
GS
component accounted for threshold adjustment implant
five
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ECE520 - Lecture 2 Slide: 23 University of New Mexico
MOSFET Threshold Voltage Components
|
|
.
|

\
|
=
i
A
F
n
N
Ln
q
KT
|
?
ox
I
ox
SS
ox
B
F ms T
C
Q
C
Q
C
Q
V + + = 2
0
ECE520 - Lecture 2 Slide: 24 University of New Mexico
MOSFET Threshold Voltage Components
Q
ox
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ECE520 - Lecture 2 Slide: 25 University of New Mexico
ox
I
ox
SS
ox
B
F ms T
C
Q
C
Q
C
Q
V + + = 2
0
MOSFET Threshold Voltage Components
?
|
|
.
|

\
|
=
i
A
F
n
N
Ln
q
KT
|
ECE520 - Lecture 2 Slide: 26 University of New Mexico
MOSFET Threshold Voltage Components
ox
F si A
B
C
qN
V
| c 2 2
=
Q
B
=
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ECE520 - Lecture 2 Slide: 27 University of New Mexico
MOSFET Threshold Voltage Components
ox
ox
ox
F si A
F ms T
C
Q
C
qN
V + + =
c

2 2
2
0
ox
ox
ox
t
C
c
=
|
|
.
|

\
|
=
i
A
F
n
N
Ln
q
KT
Where: and
But what happen Bulk and Source are at different potential?
ECE520 - Lecture 2 Slide: 28 University of New Mexico
Body Effect
ox
SB F si A
B
C
V qN
V
+
=
| c 2 2
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ECE520 - Lecture 2 Slide: 29 University of New Mexico
Body Effect
-2.5 -2 -1.5 -1 -0.5 0
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
BS
(V)
V
T

(
V
)
Key Point: Body effect raises V
T
Why does this matter?
In a stack (such as NMOS in a NAND
gate) the sources of higher devices in the
stack do not equal 0V due to resistance
of the lower transistors - this results in
lower current drive (lower Ids) due to
higher apparent V
T
Single polarity pass gates can only bring
the drain to V
DD
-V
T
Body bias can be purposely created to
lower standby power by modulating I
OFF
( )
F BS F T T
V V V 2 2
0
+ =
ECE520 - Lecture 2 Slide: 30 University of New Mexico
I
D
= -v
n
Q(x)W
Current Voltage Relation
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ECE520 - Lecture 2 Slide: 31 University of New Mexico
Current Voltage Relation
W
ECE520 - Lecture 2 Slide: 32 University of New Mexico
Device Operation: Linear Region
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ECE520 - Lecture 2 Slide: 33 University of New Mexico
Device Operation: Saturation
ECE520 - Lecture 2 Slide: 34 University of New Mexico
Device Operation: Saturation
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ECE520 - Lecture 2 Slide: 35 University of New Mexico
Device Operation: Saturation
ECE520 - Lecture 2 Slide: 36 University of New Mexico
Linear into Saturation
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ECE520 - Lecture 2 Slide: 37 University of New Mexico
Saturation Region
ECE520 - Lecture 2 Slide: 38 University of New Mexico
Saturation Region
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ECE520 - Lecture 2 Slide: 39 University of New Mexico
Saturation Region Analogy
ECE520 - Lecture 2 Slide: 40 University of New Mexico
MOSFET Parameter Measurement
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ECE520 - Lecture 2 Slide: 41 University of New Mexico
MOSFET Parameter Measurement
ECE520 - Lecture 2 Slide: 42 University of New Mexico
Channel Length Modulation
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ECE520 - Lecture 2 Slide: 43 University of New Mexico
Channel Length Modulation
ECE520 - Lecture 2 Slide: 44 University of New Mexico
Device Operation: I-V curves
( ) ( )
DS
DS
DS T GS n DS
V
V
V V V
L
W
K I +
(

' = 1
2
2
T GS DS
V V V <
( ) ( )
DS T GS
n
DS
V V V
L
W K
I +
'
= 1
2
2
T GS DS
V V V >
I
D
S
[
m
A
]
V
DS
[V]