INTRODUCTION TO I/O
INTERFACE
I/O devices work with mechanical speed where as
microprocessor works with electronics speed.
There is always speed and data type incompatibility
between them.
So, we use some devices which establish communication
between microprocessor and I/O devices.
They are called I/O ports.
They are actually high speed registers controlled by a
command register.
We can configure command register in such a manner
where in which each bit in the command register
corresponds to a bit in I/O port or each bit controls the
direction of data flow in an entire I/O port
INTRODUCTION TO I/O
INTERFACE
The I/O Instructions:
The instruction set contains one type of instruction that
transfers information to an I/O device (OUT) and
another to read information from an I/O device (IN).
The I/O address is stored in register DX as a 16-bit I/O
address or in the byte immediately following the
opcode as an 8-bit I/O address.
Intel calls the 8-bit form (p8) a fixed address because
it is stored with the instruction, usually in a ROM.
The 16-bit I/O address in DX is called a variable
address because it is stored in a DX, and then used to
address the I/O device
Example1: IN AL, p8 ; 8 A byte is input into AL from
port p8
Example 2: IN AL, DX ; 8 A byte is input into AL from
the port addressed by DX
Whenever data are transferred by using the IN or OUT
instructions, the I/O address, often called a port
number (or simply port), appears on the address
bus.
The external I/O interface decodes the port number
in the same manner that it decodes a memory address.
The 8-bit fixed port number (p8) appears on address bus
connections A7A0 with bits A15A8 equal to
000000002.
The 16-bit variable port number(DX)
appears on address connections A15
A0.
This means that the first 256 I/O port
addresses (00HFFH) are accessed by
both the fixed and variable I/O
instructions, but any I/O address from
0100H to FFFFH is only accessed by
the variable I/O address.
Isolated and Memory-Mapped I/O
There are two ways by which one can interface I/O devices to
a microprocessor.
i) I/O mapped I/O and
ii) Memory mapped I/O.
In memory mapped I/O, the 1 Mb memory that can be
interfaced to 8086/8088 itself is used to address I/O devices.
But in I/O mapped I/O there is a separate address space for I/O
devices.
The term isolated describes how the I/O locations are isolated
from the memory system in a separate I/O address space
Some important differences between I/O mapped I/O and
memory mapped I/O are listed below:
Basic Input and Output Interfaces
The basic input device is a set of three-
state buffers.
The basic output device is a set of data
latches.
The term IN refers to moving data from
the I/O device into the microprocessor and
the term OUT refers to moving data out of
the microprocessor to the I/O device.
The Basic Input Interface:
The external TTL data (simple toggle switches in this
example) are connected to the inputs of the buffers.
The outputs of the buffers connect to the data bus.
The circuit of Figure allows the microprocessor to
read the contents of the eight switches that connect
to any 8-bit section of the data bus when the select
signal SEL becomes a logic 0.
Thus, whenever the IN instruction executes, the
contents of the switches are copied into the AL
register.
When the microprocessor executes an IN
instruction, the I/O port address is decoded to
generate the logic 0 on SEL .
A 0 placed on the output control inputs (1G and
2G ) of the 74ALS244 buffer causes the data
input connections (A) to be connected to the data
output (Y) connections.
If a logic 1 is placed on the output control inputs
of the 74ALS244 buffer, the device enters the
three state high-impedance mode that effectively
disconnects the switches from the data bus.
The Basic Output Interface.
The basic output interface receives
data from the microprocessor and
usually must hold it for some
external device.
Figure shows how eight simple light-
emitting diodes (LEDs) connect to
the Microprocessor through a set of
eight data latches
When the OUT instruction executes, the data from AL, AX,
or EAX are transferred to the latch via the data bus.
Here, the D inputs of a 74ALS374 octal latch are
connected to the data bus to capture the output data, and
the Q outputs of the latch are attached to the LEDs.
When a Q output becomes a logic 0, the LED lights.
Each time that the OUT instruction executes, the SEL
signal to the latch activates, capturing the data output to
the latch from any 8-bit section of the data bus.
The data are held until the next OUT instruction executes.
Thus, whenever the output instruction is executed in this
circuit, the data from the AL register appear on the LEDs
Handshaking:
Many I/O devices accept or release information at a much
slower rate than the microprocessor.
Another method of I/O control, called handshaking or
polling, synchronizes the I/O device with the
microprocessor.
An example of a device that requires handshaking is a
parallel printer that prints a few hundred characters per
second (CPS).
It is obvious that the microprocessor can send more than
a few hundred CPS to the printer, so a way to slow the
microprocessor down to match speeds with the printer
must be developed.
data are transferred through a series of data connections (D7
D0).
BUSY indicates that the printer is busy.
STB is a clock pulse used to send data to the printer for
printing.
The ASCII data to be printed by the printer are placed on D7
D0, and a pulse is then applied to the STB connection.
The strobe signal sends or clocks the data into the printer so
that they can be printed.
As soon as the printer receives the data, it places a logic 1 on
the BUSY pin, indicating that the printer is busy printing data.
The microprocessor software polls or tests the BUSY pin to
decide whether the printer is busy
If the printer is busy, the
microprocessor waits; if it is not
busy, the microprocessor sends the
next ASCII character to the printer.
This process of interrogating the
printer, or any asynchronous device
like a printer, is called handshaking
or polling.
THE PROGRAMMABLE PERIPHERAL
INTERFACE
The 82C55 programmable peripheral interface(PPI) is a
very popular, low-cost interfacing component found in
many applications
The PPI, which has 24 pins for I/O that are
programmable in groups of12 pins, has groups that
operate in three distinct modes of operation.
The 82C55 can interface any TTL-compatible I/O device
to the microprocessor. The 82C55 can interface any
TTL-compatible I/O device to the microprocessor. The
82C55 (CMOS version) requires the insertion of wait
states if operated with a microprocessor using higher
than an 8 MHz clock
Because I/O devices are inherently slow, wait states
used during I/O transfers do not impact significantly
upon the speed of the system
Basic Description of the 82C55:
Group A connections consist of port A (PA7PA0) and the
upper half of port C (PC7PC4), and group B consists of
port B (PB7PB0) and the lower half of port C (PC3PC0).
The 82C55 is selected by its pin for programming and
for reading or writing to a port.
Register selection is accomplished through the A1and
A0 input pins that select an internal register for
programming or operation
I/O port assignments used for programming and access to the
I/O ports
The 82C55 is a fairly simple device to interface
to the microprocessor and program. For
the 82C55 to be read or written, CS the input
must be a logic 0 and the correct I/O address
must
be applied to the A1 and A0 pins. The
remaining port address pins are dont cares as
far as the
82C55 is concerned, and are externally
decoded to select the 82C55
The RESET input to the 82C55 initializes the device whenever
the microprocessor is reset.
A RESET input to the 82C55 causes all ports to be set up as
simple input ports using mode 0
operation.
After a RESET, no other commands
are needed to program the 82C55, as long as it is used as an
input device for all three ports
an 82C55 is interfaced to the personal computer at port
addresses 60H63H for keyboard
control, and also for controlling the speaker, timer, and other
internal devices such as memory
expansion. It is also used for the parallel printer port at I/O ports
378H37BH
Programming the 82C55
The 82C55 is programmed through the two internal command
registers
bit position 7 selects either command
byte A or command byte B.
Command byte A programs the
function of group A and B, whereas
command byte B sets (1) or
resets (0) bits of port C only if the
82C55 is programmed in mode 1 or
2.
Group B pins (port B and the lower part of port
C) are programmed as either input or output
pins. Group B operates in either mode 0 or mode
1. Mode 0 is the basic input/output mode that
allows the pins of group B to be programmed as
simple input and latched output connections.
Mode 1 operation is the strobed operation for
group B connections, where data are transferred
through port B and handshaking signals are
provided by port C.
Group A pins (port A and the upper
part of port C) are programmed as
either input or output
pins. The difference is that group A
can operate in modes 0, 1, and 2.
Mode 2 operation is a
bidirectional mode of operation for
port A.
If a 0 is placed in bit position 7 of the command
byte, command byte B is selected. This command
allows any bit of port C to be set (1) or reset (0), if
the 82C55 is operated in either mode 1 or 2.
Otherwise, this command byte is not used for
programming. The bit set/reset feature is often
used
in a control system to set or clear a control bit at
port C. The bit set/reset function is glitch-free,
which means that the other port C pins will not
change during the bit set/reset command.
Mode 0 Operation
Mode 0 operation causes the 82C55
to function either as a buffered input
device or as a latched
output device.
