VHDL and Processes

Defining Sequential Circuit Behavior

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 VHDL Processes
 VHDL process is the most common way to
implement sequential circuits
 A process is a sequence of statements.
 Each process is a single concurrent statement.
 All processes in a design execute concurrently.
 A process communicates with the rest of a
design via signals or ports declared outside
the process.
 Processes can define either sequential OR
combinational logic
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 Process Statements

 A process statement (or a process)

implements a sequential algorithm
 Contains both sequential and concurrent
statements
 Sequential statements are only used within a process
 Evaluation is sequential; i.e. top to bottom like
software
 Multiple assignments to the same signal may exist
 The last assignment before the end of the process is
the real assignment.

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 Sequential Statements
 The following are sequential statements.
 Assignment - assign values to variables and signals.
 Flow control - conditional execution (if and case), repeat
(for...loop, while, until), and skip (next and exit).
 Subprograms - define sequential algorithms to use
repeatedly in a design (procedure and function).
 Wait statements - describe a pause until an event occurs
 Null statements - declare that no action is necessary
 Sequential statements MUST reside within a
process

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 Process Activation and Control
 A process is activated when defined signals
change state
 Monitored signals defined in sensitivity list OR
 Monitored signals listed in WAIT statements
 Monitored signals are checked as part of
architecture evaluation
 Any change of monitored signal activates the
process.
 Process control statements determine which signal
assignments will be performed.

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 Processes with Sensitivity Lists
 Processes can be defined with an explicit
“sensitivity list”
 Sensitivity list is a list of signals that is monitored for
changes
 Sensitive processes are activated when any of the
sensitivity list signals change state
 A sensitivity list process cannot have wait statements
defined within the process
 There is an implicit “WAIT ON” statement at the end of the
process
 Process evaluation is suspended at the end of process.

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 Processes without Sensitivity Lists
 Processes can be defined without any sensitivity list
 These processes MUST have at least one WAIT
statement.
 Some tools require WAIT to be the first statement after BEGIN.
 Initial process evaluation runs until first WAIT is encountered.
 The WAIT statement defines signals that are monitored
for change.
 Non-sensitive processes are activated when WAIT
statement signals change state
 Process suspends when next WAIT statement is
encountered
 Some tools allow multiple WAIT statements per process.

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 Process Evaluation
 Once activated, process evaluation starts at point of
last suspension.
 Processes execute top to bottom
 If no WAIT is hit before the end of process, evaluation
loops back to the beginning and continues.
 Signal values referenced are those at process start.
 All signal assignments are only possible assignments.
 The last assignment before suspension is the assignment
that will be performed
 ACTUAL SIGNAL ASSIGNMENTS ARE ONLY
MADE AT THE END OF PROCESS EVALUATION!

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 Process Structure

LABEL1: process (sensitivity list <optional>)

-- declarations

begin

--process statements like

--wait on CLK, RESET;
--wait until CLK'event and CLK='1';

end process;

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 Variables

 Variables are only declared within a process

 Used for loop counters, temp storage, etc.
 Scope is only within the process
 Form is same as signal except for “VARIABLE”
keyword
 Variable assignment -
 Form is vname := expression;
 Assignment takes effect immediately

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 WAIT Statements

WAIT on sig1, sig2, …sign; Wait for event on one or

more of signals

WAIT until condition; Wait until condition is true

WAIT for timeperiod; Wait for time to elapse

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 WAIT Statements
 Wait statements can be placed anywhere in process
block
 execution proceeds until wait is encountered
 execution then suspends until wait is satisfied
 A process may have multiple wait statements
 Exception: Process with sensitivity list cannot contain
any WAIT statements!

There may be tool-related limitations; most tools do not

fully implement all process relate VHDL features

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 Conditional Process Execution

 Process execution is in-line, top to bottom

unless a conditional execution statement(s) is
encountered
 Types are similar to software constructs
 CASE
 IF THEN ELSE
 Tools may not implement all forms

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 CASE

case <expression> is

when choice1 => seq. Statements 1

when choice2 => seq. Statements 2
*
*
when others => seq. Statements others

end case;

Like the select assignment, the choices may be a single

value,a group (c1 | c2 | c3) or a range (c1 to c3)

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 IF THEN ELSE

If <condition> then
If a condition is true the
seq. Statements associate statements are
executed and the rest of the
elsif <condition> then group are skipped.

seq. Statements NOTE: the “else if” case is

ELSIF (one word, e missing)
else

seq. Statements

end if;

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 Process Iteration

 Allows repetitive execution (looping)

 Three basic forms
 loop … end loop; (infinite)
 for <var in range> loop … end loop;
 while <condition> loop … end loop;
 all may have an option label as prefix

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 NEXT

 Used to terminate current pass through loop

 Four forms
 next; (absolute)
 next when <condition>;
 next label;
 next label when <condition>;
 The last two forms allow termination to the
end of an outer loop

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 EXIT

 Used to terminate entire loop execution

 Four forms
 exit; (absolute)
 exit when <condition>;
 exit label;
 exit label when <condition>;
 The last two forms allow termination from
an inner loop to the end of an outer loop

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Combinational Logic Definition w/ Processes

 Processes can define combinational logic functions

 1) ALL signals on the right side of assignment operator
“<=“ MUST be listed in the process sensitivity list
 2) ALL input signal value combinations MUST have
signal assignments
 3) ALL output signals MUST be assigned values for
every input combination

 Failure to meet the above conditions results in

implied memory!

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 Combinational Logic Processes (cont.)

 The most common problem with defining

combination logic process is meeting
condition 2.
 An undefined input combination implies outputs
don’t change; i.e. memory is needed.
 IF, END IF statement is the greatest culprit;
there must be a “default” assignment.
 ELSE, when others, mainly used.

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 Clock Edge Detection

 You cannot just conditionalize behavior by

detecting “clk = ‘1’; we need the clock edge
 Signal attribute ‘event is used
 clk’event is true just after a clk change; false the
rest of the time
 The combination of clk’event and value
defines positive or negative clock edge
 Positive: (clk’event and clk = ‘1’)
 Negative: (clk’event and clk = ‘0’)

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 Simple Decade Counter Example
Architecture behave of deccnt is
signal cntval: std_logic_vector(3 downto 0);

cntr: process (clk, reset)

begin
if (reset = ‘1’) then
cntval <= “0000”;
elsif (clk’event and clk = ‘1’) then
cntval <= cntval + “0001”;
if (cntval = “1001”) then
cntval <= “0000”;
end if;
end if;
end process;

end behave;

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 Enumerated Type Definition

 You can define your own enumerated data

types
 Handy when defining states and transitions
 Form is:

TYPE type_name IS (value list);

 Once declared, the data type is used to define

new signals of that type

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 Enumerated Type Example
type state_type is (reset, sync, load, out);
signal pstate: state_type;

ss: process (clk)

begin
if (clk’event and clk = ‘1’) then
case pstate is
when reset => ….

when sync => ….

etc.
end if;
end process;
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 Sequential State Machines in VHDL

 The two basic techniques are:

 The 3-process definition method
 State register process, next-state combinational logic
process, output combinational logic process
 The 1-process and concurrent assignment method
 A single process defines state register and transitions
 Conditional or selected concurrent assignment define
the output combinational logic
 See text section 5.8, pp. 264 for examples of
VHDL processes.

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Real-Time State Machine Example
type state_type is (idle, init, dat, par, stop);
signal pstate: state_type;
signal baud, last: std_logic;
signal clkdiv, cntr: integer range 0 to 100000000;

begin
cd: process (clk)
begin
if (clk’event and clk = ‘0’) then
clkdiv <= clkdiv + 1;
baud <= ‘0’;
if (clkdiv >= baudiv) then
clkdiv <= 0;
baud <= ‘1’;
end if;
end if;
end process;

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Real-Time State Machine Example (cont.)
cu: process (clk, reset)
begin
if (reset = ‘1’) then
pstate <= idle;

elsif (clk’event and clk = ‘1’ and baud = ‘1’) then

case pstate is
when idle =>
if (go = ‘1’) then
pstate <= init;
endif;

when init =>

pstate <= dat;

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Real-Time State Machine Example (cont.)

when dat =>

if (last = ‘1’ and pe = ‘1’) then
pstate <= par;
elsif (last = ‘1’ and pe = ‘0’ and ns = ‘1’) then
pstate <= stop;
elsif (last = ‘1’ and pe = ‘0’ and ns = ‘0’) then
pstate <= idle;
end if;

when par =>

if (ns = ‘1’) then
pstate <= stop;
else
pstate <= idle;
end if;

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Real-Time State Machine Example (cont.)

when stop =>

pstate <= idle;
end case;
end if;
end process;

cp: process (clk)

variable lodval: integer range (0 to 7);
begin
if (clk’event and clk = ‘1’) then
if (pstate = dout) then
cntr <= cntr – 1;

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Real-Time State Machine Example (cont.)
else
lodval := 4;
if (ls(0) = ‘1’) then lodval := lodval + 1; end if;
if (ls(1) = ‘1’) then lodval := lodval + 2; end if;
cntr <= lodval;
end if;
end if;
end process;

last <= ‘1’ when (cntr = “000”) else ‘0’;

mark <= ‘1’ when (pstate = idle or pstate = stop) else ‘0’;
space <= ‘1’ when (pstate = init) else ‘0’;
dout <= ‘1’ when (pstate = dat) else ‘0’;
pout <= ‘1’ when (pstate = par) else ‘0’;

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