What is Synthesis?

Logic Synthesis is the automated process

of converting a functional model of a
system into a gate-level circuit.
 Synthesis = Translation + Optimization +Mapping

If s0 = 1’b0 & s1 = 1’b0; Translate

y = x0;
else if
s0 = 1’b0 & s1 = 1’b1; Optimize + Map
y = x1;
else if
s0 = 1’b1 & s1 = 1’b0;
y = x2;
else
s0 = 1’b1 & s1 = 1’b1;
y = x3;

HDL Source

Generic Boolean
(GTECH) Target Technology
Logic Synthesis Flow

RTL Description

Translation

Unoptimized Intermediate
Representation

Logic Optimization

Technology Library Technology Mapping Design Constraints

&
Optimization

Optimized Gate Level Netlist

 Why Synthesis is required?
Benefits of synthesis:
– High level design entry
– Increased designer productivity
– Reduction of layout design expertise
requirement
– Improved quality
– Technology independence
– Facilitates design re-use and sharing
AND GATE

SYNTHESIS = TRANSILATION + OPTIMIZATION + MAPPING

module and2 (z, a, b);

a
output z;
input a, b; z

b
always @ (a or b)
if (a == 1 and b == 1)
z <= 1;
else
z <= 0;

endmodule
OR GATE

TRANSILATION
module or2 (z, a, b); a
z
output z;
input a, b; b

always @ (a or b)
if (a == 0 and b == 0)
OPTIMIZATION
z <= 0; a
else
z <= 1; z

b
endmodule
D-FLIP FLOP

module cnt (q, d, clk, rst); module cnt (q, d, clk, rst);

output q; output q;
input d, clk, rst; input d, clk, rst;

reg q; reg q;

always @ (posedge clk) always @ (posedge clk or posedge rst)

if (rst) if (rst)
q <= 0; q <= 0;
else else
q <= d; q <= d;

endmodule endmodule
COUNTER

module cnt (cout, clk, rst);

+1
output [3:0] cout;
input clk, rst;

reg [3:0] cout;

0 4 4
always @ (posedge clk) d q
‘0’ 1
if (rst)
cout <= 4’b0; clk
else
cout <= cout + 1’b1; rst

endmodule
 Code for Synthesis

Code that is functionally equivalent, but coded differently, will give

different synthesis results.

You cannot rely solely on Tool to fix a poorly coded design.

Try to understand the hardware you are describing, to give tool the
best possible starting point.
 Optimization

Optimization can occur at each of three levels:

Architectural High Level Synthesis

Logic Level Structure & Flatten

Gate Level Mapping

Optimized Netlist
Order and Group Arithmetic Functions

Statement1: ADD = A1 + A2 + A3 + A4;

A1

A2 +
A3 +
A4
+ ADD

A1 Statement2: ADD = (A1 + A2) + (A3 +

A2
+ A4);

+ ADD
A3

A4
+
 Mapping

• High-level synthesis is Constraint-Driven.

• High-level synthesis is based on design constraints and coding style

• Tool makes high-level synthesis decisions to produce area-efficient

results that meet timing.

• High-level Synthesis takes place only when optimizing an

unmapped design
– It will not occur when reoptimizing a gete-level netlist.
– Exception: Incremental implementation selection can recur after
mapping to gates.
Combinational Mapping
Steps Involved in Synthesis

 Setup Technology Environment

 Read the Design
 Set Constraints
 Performance Optimization
 Generate Reports
 Generate Output Files
Inputs and Outputs of the RTL Complier

Inputs :
• RTL : Verilog ,VHDL
• Constraints : .SDC or .g
• Library : .lib

Outputs:
• Optimized netlist
• Constraints : .SDC or .g
Thank You
 Resource Sharing

module res_sharing (A1, B1, C1, D1, COND_1, Z1);

input COND_1;
input [7:0] A1, B1, C1, D1;
output [7:0] Z1;
reg [7:0] Z1;

always @(A1 or B1 or C1 or D1 or COND_1)

begin
if (COND_1)
Z1 <= A1 + B1;
else
Z1 <= C1 + D1;
end
COND_1
endmodule

A1

B1
+ 1

Z1
0
C1
+
D1
 Resource Sharing

module res_sharing (A1, B1, C1, D1, COND_1, Z1);

input COND_1;
input [7:0] A1, B1, C1, D1;
output [7:0] Z1;
wire [7:0] Z1;
reg [7:0] z_temp1, z_temp2;

always @(A1 or B1 or C1 or D1 or COND_1)

if (COND_1)
A1
begin
z_temp1 <= A1;
z_temp2 <= B1; C1
end
else COND_1 + Z1
begin B1
z_temp1 <= C1;
z_temp2 <= D1;
end D1

assign Z1 = z_temp1 + z_temp2;

endmodule
Order and Group Arithmetic Functions

A1

A2 +
A3 +
A4
+ ADD

Statement1
A1

A2
+
+ ADD
A3

A4
+ Statement2
Order and Group Arithmetic Functions

The ordering and grouping of arithmetic functions can influence

design performance.

For Verilog, the following two statements are not necessarily

equivalent.

Statement1: ADD = A1 + A2 + A3 + A4;

Statement2: ADD = (A1 + A2) + (A3 + A4);

The first statement cascades three adders in series. The second

statement creates two adders in parallel: A1 + A2 and A3 + A4. In
the second statement, the two additions are evaluated in parallel
and the results are combined with a third adder. RTL simulation
results are the same for both statements, however, the second
statement results in a faster circuit after synthesis (depending on
the bit width of the input signals).
 Resource Sharing

Resource sharing is an optimization technique that uses a single

functional block (such as an adder or comparator) to implement
several operators in the HDL code. Use resource sharing to
improve design performance by reducing the gate count and the
routing congestion. If you do not use resource sharing, each HDL
operation is built with separate circuitry. However, you may want to
disable resource sharing for speed critical paths in your design.

The following operators can be shared either with instances of the

same operator or with an operator on the same line.
*
+-
> >= < <=

For example, a + operator can be shared with instances of other +

operators or with - operators. A * operator can be shared only with
other * operators.
Order and Group Arithmetic Functions

Although the second statement generally results in a faster circuit,

in some cases, you may want to use the first statement. For
example, if the A4 signal reaches the adder later than the other
signals, the first statement produces a faster implementation
because the cascaded structure creates fewer logic levels for A4.
This structure allows A4 to catch up to the other signals. In this
case, A1 is the fastest signal followed by A2 and A3; A4 is the
slowest signal.

Most synthesis tools can balance or restructure the arithmetic

operator tree if timing constraints require it. However, it is
recommended that you code your design for your selected
structure.
Multiple Architectures for each Macro

Ripple Carry

Ripple Carry-Select

+
Carry Look Ahead

Carry Save
Logic Synthesis
using
RTL Compiler

By Mr. Lingaiah
RTL Compiler Synthesis Flow
Setup Environment, Read Design & Elaborate
Setup Technology Environment
This library attribute specifies the target technology for synthesis .
To load the library ,enter
set_attr library slow.lib

To load multiple libraries ,enter

set_attr library slow.lib typical.lib fast.lib

Read the Design

The command used to read the RTL is
read_hdl { file1.v file2.v }

The elaborate command

• Builds data structure
• Performs high level HDL optimization
• Here the design is targeted to the generic technology independent
library
Check Design and Specify Constraints

Checking for design Issues

The check_design is used to check the design problems such

as undriven or multi driven ports, unloaded sequential elements
,unresolved references and any assign statements in the design .
syntax : check_design –all

Specifying Design Constraints

We can read the sdc file using the command :
read_sdc <sdc file name >
Design Constraints

Defining a clock :

The create_clock SDC command is used to define the clock

objects and their associated details like waveform
create_clock –period 2 –name CLK –waveform {0 1 } [get_port CLK]
Input and Output Delays

The following SDC commands constrain the input and output ports
set_input_delay –clock clk1 0.2 [all_inputs]
set_output_delay –clock clk2 0.4 [all_outputs]
Checking for Missing Constraints

• Use report timing –lint to check for missing

constraints. Always run this command and review
the log file before synthesis.

• Refer to the table generated at the end of read_sdc,

but always review the log file for warnings and
errors that are listed prior to the table.

• The SDC warnings can be easily traced in a log file

by searching for the keyword SDC.
Checking for Missing Constraints

• Here are some examples of missing constraint warnings:

Synthesizing the Design

• The goal of synthesis is to provide the smallest possible implementation of the

design while meeting timing and power constraints. Use the synthesize command to
run synthesis

• synthesize [–to_generic] [–to_mapped] [-effort <level>]

[-incremental] [design|sub-design]

• –to_generic: Generic optimizations such as MUX and datapath optimizations are

done in this stage.
• -to_mapped :Maps the specified design(s) to the cells described in the supplied
technology library and performs logic optimization.

• -effort <level>—Can be low, medium (default) or high.

• -incremental: to achieve the timing goals of the design. To correct any timing
problems(critical region resynthesis for timing )and to correct DRC iteratively
Generic Synthesis Timing Reports (Report
timing)
 Mapped Synthesis Timing Reports (Report
timing)
 Ungrouping Objects

• Ungrouping flattens a level of hierarchy

• Hierarchical ungrouping can improve timing by giving the
compiler a wider scope of optimization.
• If you need to ungroup the design hierarchy
CRITICAL_GROUP (which contains instances I1 and I2),
use the ungroup command along with the instance name
as shown below

• ungroup [find / -instance CRITICAL_GROUP]

Analyzing the Synthesis Results

• After synthesizing the design, you can generate detailed

timing and area reports using the various report
commands.
• To generated a detailed area report, use report area.

• To generate a detailed gate selection, use report gates.

• To generate a detailed timing report, including the worst

critical path of the current design, use report timing.
Generating reports

• The last step in the flow involves writing out the gate-level
net list, SDC, for processing in your place and route tool.

• To write the gate-level net list, use the write_hdl command

write_hdl > XYZ.vg

• To write the design constraints in SDC format, use the

write_sdc command.
write_sdc > XYZ.sdc
THANK YOU