Hacettepe University

ELE 225 Fundamentals of Digital

Systems

Chapter 6:
Registers and Counters

Assoc. Prof. S. Esen Yüksel

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Topics

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 Previously on ELE 225
We learned how to
Distinguish a sequential circuit from a combinational circuit.
Realize the SR latch, transparent latch, D flip-flop, JK flip-

flop, and T flip-flop.

Use the characteristic table and characteristic equation of a

flip-flop.
Derive the state equation, state table, and state diagram of

a clocked sequential circuit.

Distinguish between Mealy and Moore finite state

machines.
Eliminate equivalent states in a state table.

Define different codes for the binary state assignment.

Design a sequential circuit with D, JK, and T flip-flops.

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 Chapter Objectives
 Understand the use, functionality, and
modes of operation of registers, shift
registers, and universal shift registers.
 Know how to properly create the effect of
a gated clock.
 Understand the structure and
functionality of a serial adder circuit.
 Know how to analyze and design a ripple
counter, synchronous counter, ring
counter, and Johnson counter.
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 Chapter 6 Registers and
Counters
 The flip-flops are essential components in
clocked sequential circuits.
 Circuits that include flip-flops are usually
classified by the function they perform.
Two such circuits are registers and
counters.
 An n-bit register consists of a group of n
flip-flops capable of storing n bits of
binary information.
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 6-1 Registers
 In its broadest definition, a register
consists a group of flip-flops and gates
that affect their transition.
 The flip-flops hold the binary information.
 The gates determine how the information is
transferred into the register.
 Counters are a special type of register.
 A counter goes through a predetermined
sequence of states.

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 6-1 Registers
 Fig 6-1 shows a
register constructed
with four D-type flip-
flops.
 “Clock” triggers all
flip-flops on the
positive edge of each
pulse.
 “Clear” is useful for
clearing the register
to all 0’s prior to its
clocked operation. 7
 Register with Parallel Load
 A clock edge applied to the C inputs of
the register of Fig. 6-1 will load all four
inputs in parallel.
 For synchronism, it is advisable to control
the operation of the register with the D
inputs rather than controlling the clock in
the C inputs of the flip-flops.
 A 4-bit register with a load control input
that is directed through gates and into the
D inputs of the flip-flops is shown in Fig. 6-
2.
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Register with Parallel Load

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 Register with Parallel Load
 When the load input is
1, the data in the four
inputs are transferred
into the register with
next positive edge of
the clock.
 When the load input is
0, the outputs of the
flip-flops are
connected to their
respective inputs.
 The feedback
connection from
output to input is
necessary because
the D flip-flops does
not have a “no 10
 6-2 Shift Registers
 A register capable of shifting its binary
information in one or both direction is
called a shift register.
 All flip-flops receive common clock pulses,
which activate the shift from one stage to
the next.
 The simplest possible shift register is one
that uses only flip-flops, as shown in Fig.
6-3.

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 Shift Registers

 Each clock pulse shifts the contents of the

register one bit position to the right.
 The serial input determines what goes into the
leftmost flip-flop during the shift.
 The serial output is taken from the output of the
rightmost flip-flop. 12
 Serial Transfer
 A digital system is said to operate in a
serial mode when information is
transferred and manipulated one bit at a
time.
 This in contrast to parallel transfer where
all the bits of the register are transferred
at the same time.
 The serial transfer us done with shift
registers, as shown in the block diagram
of Fig. 6-4(a).
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 Serial Transfer

 To prevent the loss of information stored in the source

register, the information in register A is made to circulate
by connecting the serial output to its serial input.
 The shift control input determines when and how many
times the registers are shifted. This is done with an AND
gate that allows clock pulses to pass into the CLK
terminals only when the shift control is active. [Fig. 6- 14
 Serial Transfer

 The shift control signal is synchronized with the clock and

changes value just after the negative edge of the clock.
 Each rising edge of the pulse causes a shift in both
registers. The fourth pulse changes the shift control to 0
and the shift registers are disabled. 15
 Serial Transfer
Table 6-1
Serial-Transfer Example
Timing Pulse Shift Register Shift Register
A B
Initial value 1011 0010

After T1 1101 1001

After T2 1110 1100

After T3 0111 0110

After T4 1011 1011

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 Serial Transfer
 In the parallel mode, information is
available from all bits can be transferred
simultaneously during one clock pulse.
 In the serial mode, the registers have a
single serial input and a single serial
output. The information us transferred
one bit at a time while the registers are
shifted in the same direction.

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 Serial Addition
 Operations in digital computers are
usually done in parallel because this is a
faster mode of operation.
 Serial operations are slower, but have the
advantage of requiring less equipment.
 The two binary numbers to be added
serially are stored in two shift registers.
 Bits are added one pair at a time through
a single full adder. [Fig. 6-5]

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Serial Addition

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 Serial Addition
 By shifting the sum into A while the bits of
A are shifted out, it is possible to use one
register for storing both the augend and
sum bits.
 The carry out of the full adder is
transferred to a D flip-flop.
 The output of the D flip-flop is then used
as carry input for the next pair of
significant bits.

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 Serial Addition
 To show that serial operations can be
designed by means of sequential circuit
procedure, we will redesign the serial adder
using a state table.
 The serial outputs from registers are
designated by x and y.
 The sequential circuit proper has two inputs, x
and y, that provide a pair of significant bits,
an output S that generates the sum bit, and
flip-flop Q for storing the carry. [Table. 6-2]

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 Serial Addition
Table 6-2
State Table for serial Adder

Present Inputs Next State Output Flip-Flop

State Inputs
Q X y Q S JQ KQ
0 0 0 0 0 0 X
0 0 1 0 1 0 X
0 1 0 0 1 0 X
0 1 1 1 0 1 X
1 0 0 0 1 X 1
1 0 1 1 0 X 0
1 1 0 1 0 X 0
1 1 1 1 1 X 0
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 Serial Addition
 The two flip-flop input equations and the
output equation can be simplified by
means of map to obtain
 JQ = xy
 KQ = x’y’=(x+y)’
 S=x⊕y⊕Q
 The circuit diagram is shown in [Fig. 6-6]

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Serial Addition

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 Universal Shift Register
 A clear control to clear the register to 0.
 A clock input to synchronize the
operations.
 A shift-right control to enable the shift
operation and the serial input and output
lines associated with the shift right.
 A shift-left control to enable the shift
operation and the serial input and output
lines associated with the shift left.

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 Universal Shift Register
 A parallel-load control to enable a parallel
transfer and the n input lines associated
with the parallel transfer.
 n parallel output lines.
 A control state that leaves the information
in the register unchanged in the presence
of the clock.
 If the register has both shifts and parallel
load capabilities, it is referred to as a
universal shift register.
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Universal Shift Register

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Universal Shift Register

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 Universal Shift Register
 Shift registers are often used to interface
digital system situated remotely from
each other.
 If the distance is far, it will be expensive
to use n lines to transmit the n bits in
parallel.
 Transmitter performs a parallel-to-serial
conversion of data and the receiver does
a serial-to-parallel conversion.

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 6-3 Ripple Counters
 A register that goes through a prescribed
sequence of states upon the application
of input pulse is called a counter.
 A counter that follows the binary number
sequence is called a binary counter.
 Counters are available in two categories
 Ripple counters
 Synchronous counters

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 Binary Ripple Counter
 The output of each flip-flop is connected to
the C input of the next flip-flop in sequence.
 The flip-flop holding the last significant bit
receives the incoming count pulse.
 A complementing flip-flop can be obtained
from:
 JK flip-flop with the J and K inputs tied together.
 T flip-flop.
 D flip-flop with the complement output
connected to the D input. [Fig. 6-8]

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32
 Binary Ripple Counter
Table 6.4
Binary Count Sequence

A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
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 BCD Ripple Counter
 A decimal counter follows a sequence of
ten states and returns to 0 after the count
of 9.
 This is similar to a binary counter, except
that the state after 1001 is 0000.
 The operation of the counter can be
explained by a list of conditions for flip-
flop transitions.

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BCD Ripple Counter

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 BCD Ripple Counter
 The four outputs are designated by
the letter symbol Q with a numeric
subscript equal to the binary weight of
the corresponding bit in the BCD code.

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 BCD Ripple Counter
 The BCD counter of [Fig. 6-9] is a decade
counter.
 To count in decimal from 0 to 999, we
need a three-decade counter. [Fig. 6-11]
 Multiple decade counters can be
constructed by connecting BCD counters
is cascade, one for each decade.

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BCD Ripple Counter

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 6-4 Synchronous Counters
 Synchronous counters are different
from ripple counters in that clock pulses
are applied to the inputs of all flip-flops.
 A common clock triggers all flip-flops
simultaneously rather than one at a time
in succession as in a ripple counter.

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 Binary Counter
 The design of a
synchronous binary
counter is so simple
that there is no
need to go through
a sequential logic
design process.
 Synchronous binary
counters have a
regular pattern and
can be constructed
with complementing
flip-flop and gates.

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 Up-Down Binary Counter
 The two operations
can be combined in
one circuit to form
a counter capable
of counting up or
down.
 It has an up control
input and down
control input.

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 BCD Counter
 Because of the return to 0 after a count of
9, a BCD counter does not have a regular
pattern as in a straight binary count.
 To derive the circuit of a BCD synchronous
counter, it is necessary to go through a
sequential circuit design procedure.

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 BCD Counter
Table 6-5
State Table for BCD Counter
Present State Next State Output Flip-Flop inputs
Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 y TQ8 TQ4 TQ2 TQ1
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 01 0 0 1
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 BCD Counter
 The flip flop input equations can be
simplified by means of maps. The simplified
functions are

TQ1=1

TQ2=Q8’Q1

TQ4=Q2Q1

TQ8=Q8Q1+Q4Q2Q1

y=Q8Q1
 The circuit can be easily drawn with four T
flip-flops, five AND gates, and one OR gate.
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 Binary Counter with Parallel
Load
 Counters employed in digital systems
quite often require a parallel load
capability for transferring an initial binary
number into the counter prior to count
operation.
 The input load control when equal to 1
disables the count operation and causes a
transfer of data from the four data inputs
into the four flip-flops [Fig. 6-14].

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Binary Counter with Parallel
Load

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Binary Counter with Parallel
Load

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 Binary Counter with Parallel
Load
 A counter with parallel load can be used
to generate any desired count sequence.
 [Fig.6-15] shows two ways in which a
counter with parallel load is used to
generate the BCD count.

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Load to Achieve a BCD
Counter

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Binary Counter with Parallel
Load

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 Load to Achieve a BCD
Counter
 The AND gate detects the occurrence
of state 1001. The counter is initially
cleared to 0, and then the Clear and
Count inputs are set to 1, so the
counter is active at all times.
 As long as the output of the AND gate
is 0, each positive‐edge clock
increments the counter by 1.

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 Binary Counter with Parallel Load
to Achieve a BCD Counter
 When the output reaches the count of 1001,
both A0 and A3 become 1, making the
output of the AND gate equal to 1.
 This activates the Load input; and on the
next clock edge the register does not count,
but is loaded from its four inputs. Since all
four inputs are connected to logic 0, an all‐
0’s value is loaded into the register following
the count of 1001. Thus, the circuit goes
through the count from 0000 through 1001
and back to 0000 as in a BCD counter
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 Alternative option
 In Fig. 6.15 (b), the NAND gate detects the
count of 1010, but as soon as this count
occurs, the register is cleared. The count
1010 has no chance of staying on for any
appreciable time, because the register goes
immediately to 0. A momentary spike occurs
in output A0 as the count goes from 1010 to
1011 and immediately to 0000.
 The spike may be undesirable.
 Not commended.

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 6-5 Other Counters
 Counters can be designed to generate any
desired sequence of states.
 A divide‐by‐N counter (also known as a
modulo‐N counter) is a counter that goes
through a repeated sequence of N states.
 The sequence may follow the binary count or may be
any other arbitrary sequence.
 Counters are used to generate timing signals to
control the sequence of operations in a digital
system.
 Counters can be constructed also by means of
shift registers.
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 Counter with Unused
States
 Once the circuit is designed and
constructed, outside interference may
cause the circuit to enter one of the unused
state.
 If the unused states are treated as don’t-
care conditions, then once the circuit is
designed, it must be investigated to
determine the effect of the unused states
 The next state from an unused state can be
determined from the analysis of the circuit
after it is design.
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 Counter with Unused
States
Table 6-7
State Table for Counter
Present Next state Flip-Flop Inputs
State
A B C A B C JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X

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 Counter with Unused
States
 The count has a repeated sequence of six
states.
 The simplified equations are:
 JA=B KA=B
 JB=C KB=1
 JC=B’ KC=1
 The logic diagram and state diagram is
shown in [Fig. 6-16]

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Counter with Unused
States

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 Counter with Unused
States
 If this circuit goes to one of the unused
states, the next count pulse transfers it to
one of the valid states and the circuit
continues to count correctly.
 This counter is self‐correcting.
 In a self‐correcting counter, if the counter happens
to be in one of the unused states, it eventually
reaches the normal count sequence after one or
more clock pulses.
 An alternative design could use additional
logic to direct every unused state to a
specific next state. 59
 Ring Counter
 A ring counter is a circular shift register with
only one flip-flop being set at any particular
time, all others are cleared.

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 Ring Counter
 The single bit is shifted from one flip-flop
to the next to produce the sequence of
timing signals. [Fig. 6-17(a)] [Fig. 6-17(c)]
 The initial value of the register is 1000 and
requires Preset/Clear flip‐flops.
 For an alternative design, the decoder
shown in [Fig. 6-17(b)] decodes the four
states of the counter and generates the
required sequence of timing signals.

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Ring Counter

62
 Johnson Counter
 Generate the timing signals with a combination of a
shift register and a decoder, which is called a Johnson
counter.
 The number of flip‐flops will be less than that in a ring
counter, and the decoder requires only two‐input gates.
 The number of states can be doubled if the shift register
is connected as a switch-tail ring counter. [Fig. 6-18(a)]

A switch‐tail ring counter is a circular shift register with the
complemented output of the last flip‐flop connected to the
input of the first flip‐flop.
 Starting from a cleared state, the switch-tail ring
counter goes through a sequence of eight states, as
shown in [Fig. 6-18(b)].
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 Johnson Counter
 Previous circuits generate 4 timing
signals. To generate 2^n timing
signals, you can use a Johnson counter.
 JC uses a shifter register and a
decoder. The decoder can be
implemented with AND gates.
 A k-bit counter circulates a single bit
among the FFs to provide k
distinguishable states.
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Johnson Counter

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 Johnson Counter
 A Johnson counter is a k-bit switch-tail ring
counter with 2k decoding gates to provide
outputs for 2k timing signals.
 The decoding of a k-bit switch-tail ring
counter to obtain 2k timing signals follows
a regular pattern.
 Johnson counters can be constructed for
any number of timing sequences.

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 Johnson Counter
 One disadvantage of the circuit in Fig.
6.18 (a) is that if it finds itself in an
unused state, it will move from one
invalid state to another and never find its
way to a valid state.
 One correcting procedure is to disconnect
the output from FF B that goes to the D input
of FF C , and instead enable the input of FF C
by the function DC = (A +C )B.

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