SOFTWARE

ARCHITECTURE OF THE
68000

Microprocessor : Notes 3
 CHAPTER
OUTLINE

Assembly Language Programming

68000 Addressing Modes
The 68000’s Instruction Set
Subroutine and Stack
Interrupts
 THE 68000’S
INSTRUCTION SET
• Data transfer instruction
– Example MOVE
• Take data from memory – load operation

MOVE.W $10000, D1 ;Move word from $10000 to D1

D1 FE ED BE EF D1 FE ED 42 51

010000 42 51 010000 42 51
010002 55 13 010002 55 13
 THE 68000’S INSTRUCTION
SET (CONT..)
• MOVE.L $10000, D1 ;Move longword from $10000 to
FE
D1 D1 ED BE EF D142 51 55 13

010000 42 51 010000 42 51
010002 55 13 010002 55 13

• MOVE.B $10000, D1 ;Move byte from $10000 to

FE
D1 D1 ED BE EF D1FE ED BE 42

010000 42 51 010000 42 51
010002 55 13 010002 55 13
 THE 68000’S INSTRUCTION
SET (CONT..)
– Example MOVE
• Store data into memory – Store operation

MOVE.W D1, $2000 ;Move word from D1 to $2000

D1 FE ED BE EF D1 FE ED BE EF

002000 42 51 002000 BE EF
002002 55 13 002002 55 13
 THE 68000’S INSTRUCTION
SET (CONT..)
• MOVE.L D1, $2000 ;Move longword from D1 to
$2000FED1 ED BE EF D1FE ED BE EF

002000 42 51 002000 FE ED
002002 55 13 002002 BE EF

• MOVE.B D1, $2000 ;Move byte from D1 to

$2000FED1 ED BE EF D1FE ED BE EF

002000 42 51 002000 EF 51
002002 55 13 002002 55 13
 THE 68000’S INSTRUCTION
SET (CONT..)
• Moving data from memory to other memory location
– MOVE.W $1000, $1006 ; move word from $1000 to
$1006

001000 42 51 001000 42 51
001002 55 13 001002 55 13
001004 01 02 001004 01 02
001006 90 AB 001006 42 51
 THE 68000’S INSTRUCTION
SET (CONT..)
• It is a short form of the move instruction for transferring an immediate
operand to a data register.
• The immediate operand is limited to the range of –128 to 127
• The operation size is implied to be long word.
• Therefore, the 8-bit immediate operand is sign-extended to 32 bits
before being loaded into the destination, which must be a data
register

Example: MOVEQ #$F1, D1

D1 12 34 56 78 D1 FF FF FF F1
 THE 68000’S INSTRUCTION
SET (CONT..)
• EXG Instruction

EXG D1, D5 ;interchange the contents of two

registers

D1 12 12 20 30 D1 00 FF 48 7C

D5 00 FF 48 7C D5 12 12 20 30
 THE 68000’S INSTRUCTION
SET (CONT..)
• SWAP Instruction

Exchange the lower word of the specified data register

with its upper word.

SWAP D1

D1 12 34 20 30 D1 20 30 12 34
 THE 68000’S INSTRUCTION
SET (CONT..)
• LEA Instruction – Load effective address

Transfers the source operand address rather than its

content to the destination address register.
(Always generated 32-bit address).

Example 1: LEA $00200001, A0

(Same as MOVEA.L #$00200001,
A0

A0 12 34 56 78 A0 00 20 00 01
 THE 68000’S INSTRUCTION
SET (CONT..)
Example 2: LEA (A1), A0 (Same as MOVEA.L A1, A0)

A0 00 12 70 02 A0 00 10 FF FF

A1 00 10 FF FF A1 00 10 FF FF

Example 3: LEA 8(A0), A1 (No equivalent MOVEA

inst.) 00
A0 12 70 02 A0 00 12 70 02

A1 11 10 FF FF A1 00 12 70 0A
 THE 68000’S INSTRUCTION
SET (CONT..)
Example 3: LEA 8(A0, D4.L), A1 (No equivalent MOVEA inst.)

D4 00 00 20 00 D4 00 00 20 00

A0 00 12 70 02 A0 00 12 70 02

A1 00 10 FF FF A1 00 12 90 0A
 THE 68000’S INSTRUCTION
SET (CONT..)
• MOVEM Instruction – Load effective address

Moves the contents of selected registers to or from consecutive

memory locations starting at the location specified by the effective
address.
(size = word, longword

Example 1: MOVEM D0-D3,

$200055D0 55 66 66
002000 66 66
D1 77 77 88 88 002002 88 88
002004 AA AA
D2 99 99 AA AA
002006 CC CC
D3 BB BB CC CC
 THE 68000’S INSTRUCTION
SET (CONT..)
• Arithmetic Instruction
– ADD instruction – adds the source operand to the destination
operand using binary addition, and store the result in the
destination location (size = byte, word, longword)
– Note: one of the operand must be data register
– Example: ADD.W D1, D3

D1 12 34 56 78 D1 12 34 56 78

D3 FD CC 01 23 D3 FD CC 57 9B
 THE 68000’S INSTRUCTION
SET (CONT..)
• Carry Production
– For unsigned integers that range for the size byte is from 0 to
255.

Decimal Binary

255 11111111
254 11111110
: :
128 10000000
127 01111111
: :
1 00000001
0 00000000
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: ADD.B D0,
D3
1. Before execute: D0 = 128 2. D0 = 128
D3 = 15 3. D3 = 143

128 10000000 128 10000000

15 00001111 143 10001111

143 10001111 143 (1)00001111

No carry Result has 9 bit
flag C = 0 flag C = 1
after after addition
addition
 THE 68000’S INSTRUCTION
SET (CONT..)
• Overflow Production
– For signed integers that range for the size byte is -128 to
+127.

Decimal Binary

+127 01111111
: :
0 00000000
-1 11111111
: :
-127 10000001
-128 10000000
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: ADD.B D0,
D3
1. Before execute: D0 = 30 2. D0 = -3
D3 = 30 3. D3 = -
2

30 00011110 -2 11111110
30 00011110 -3 11111101
60 00111100 -5 (1) 11111011

after addition after addition

C = 0, V = 0 C = 1, V = 0
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: ADD.B D0,
D3
1. Before execute: D0 = 2 2. D0 = -2
D3 = 127 3. D3 = -127

127 01111111 -127 10000001

2 00000010 11111110

-2
after addition after addition
C129
= 0, V = 10000001
1 -129
C = 1, V(1)01111111
=1
 THE 68000’S INSTRUCTION
SET (CONT..)
• ADDA instruction
– Adds the source operand to the destination address register, and
stores the result in the address register. (size = word, longword)
– Example: ADDA.L #$70, A0

A0 00 00 20 30 A0 00 00 20 A0
 THE 68000’S INSTRUCTION
SET (CONT..)
• ADDQ instruction
– Immediate addition operation
– Operand source is (1 – 8) in immediate mode only
– Destination operand = any address mode

– Example: ADDQ #3, D6

D6 12 34 56 FF D6 12 34 57 02

ADDQ Vs MOVEQ
Source 1 .. 8 -128 .. 127
Destination Any Dn only
Data size B, W, L only
L
 THE 68000’S INSTRUCTION
SET (CONT..)
• Sub Instruction
– Destination Destination - Source

Example: D3, D1
(One of the operand has to be data register)
SUB.B

D1 12 34 56 78 D1 12 34 56 55

D3 FD CC 01 23 D3 FD CC 01 23
 THE 68000’S INSTRUCTION
SET (CONT..)
• The effect for V flag after ADD/SUB instruction
– For ADD s, d
– V = 1 if addition for 2 value have the same signed to change the
destination sign.

s d Answer (d) Overflow

Nothing happen
Positive Negative Any (Always V=0)
Nothing happen
Negative Positive Any (Always V=0)
Positive V=0
Positive Positive V=1
Negative
Negative V=0
Negative Negative V=1
Positive
 THE 68000’S INSTRUCTION
SET (CONT..)
• The effect for V flag after ADD/SUB instruction
– For SUB s, d
– V = 1 if addition for 2 value have the same signed to change the
destination sign.

s d Answer (d) Overflow

Nothing happen
Positive Positive Any (Always V=0)
Nothing happen
Negative Negative Any (Always V=0)
Positive V=0
Negative Positive V=1
Negative
Negative V=0
Positive Negative V=1
Positive
 THE 68000’S INSTRUCTION
SET (CONT..)
• The effect of flag after SUB
– C = Set to assume that 2 of the value is unsigned
– V = Set to assume that 2 of the value is signed
– Z = Set if product is 0
– N = Same as MSB
– X = Same as C
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: SUB D1,
D0
D0 before SUB D1 before SUB D0 after SUB XNZVC
D0 00 00 30 40 D1 00 00 00 02 D0 00 00 30 3E 0 0 0 0 0

D0 00 00 00 40 D1 00 00 00 40 D0 00 00 00 00 0 0 1 0 0

D0 00 00 FF FF D1 00 00 55 AA D0 00 00 AA 55 0 1 0 0 0

D0 00 00 00 00 D1 00 00 03 00 D0 00 00 FD 00 1 0 1 0 1

D0 00 00 90 00 D1 00 00 70 00 D0 00 00 20 00 0 0 0 1 0

D0 00 00 70 00 D1 00 00 90 00 D0 00 00 E0 00 1 1 0 1 1
 THE 68000’S INSTRUCTION
SET (CONT..)
• SUBQ instruction
– Immediate subtraction operation
– Operand source is (1 – 8) in immediate mode only
– Destination operand = any address mode

– Example: SUBQ #7, D6

D6 12 34 56 FF D6 12 34 56 F8

ADDQ Vs MOVEQ
Source 1 .. 8 -128 .. 127
Destination Any Dn only
Data size B, W, L only
L
 THE 68000’S INSTRUCTION
SET (CONT..)
• Multiplication Instruction
– Operand interpreted as unsigned numbers
• MULU Source, Dn
– Operand interpreted as signed numbers
• MULS Source, Dn
– Source = 16bit, any address mode
– Destination = 16 bit data register
– Multiply product = 32 bit, stored in destination data
register
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example:
MOVE.W #256, D3
#2, D3
MULU.W

D3 FD CC 01 00 D3 00 00 02 00

16 bit 32 bit
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example:
MOVE.W #FFFF, D3
# -1, D3
MULS.W

D3 FD CC FF FF D3 00 00 00 01

16 bit 32 bit
 THE 68000’S INSTRUCTION
SET (CONT..)
• Division Instruction
– Operand interpreted as unsigned numbers
• DIVU Source, Dn
– Operand interpreted as signed numbers
• DIVS Source, Dn
– Source = 16bit, any address mode
– Destination = 32 bit data register
– Division product stored in lower word destination data
register
– Remainder stored in upper word destination data
register
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example:
DIVU D0, D3

D0 FE CC 01 00 D0 FE CC 01 00

D3 00 10 00 01 D3 00 01 10 00

Remainder division

product
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example:
DIVS D0, D3

D0 FE CC 00 12 D0 00 00 00 00

D3 FF FF FE 00 D3 FF F8 FF E4

Remainder division

product
 THE 68000’S INSTRUCTION
SET (CONT..)
• NEG instruction (Negate)
– NEG instruction form the 2’s complement of the
destination operand , effectively reversing its sign

Example: NEG.W D5

D5 34 67 00 F0 D5 34 67 FF 10
 THE 68000’S INSTRUCTION
SET (CONT..)
• EXT instruction (Sign Extend)
– EXT instruction converts a byte or word register
operand to a word or long word by extending the sign
bit of the operand. Signed bit (bit 7) is copied to above
byte (bit 8 until 15).

Example 1 : EXT.W D5

D5 34 67 00 F0 34
D5 67 FF F0

D5 34 67 20 65 34
D5 67 00 65

15 8 7 0
S
 THE 68000’S INSTRUCTION
SET (CONT..)
Example 2 : EXT.L D5

D5 34 67 30 F0 D5 00 00 30 F0

D5 34 27 99 65 D5 FF FF 99 65

15 16 15 0

S
 THE 68000’S INSTRUCTION
SET (CONT..)
• Compare and Test Instruction
– CMP – Compare
• Subtract the source operand from the destination data register
and sets the condition codes according to the result; the data
register is not changed. The size of the operation can be byte,
word or longword.

• Condition codes:
– X - Not affected
– N - Set if the result is negative. Cleared otherwise
– Z - Set if the result is zero. Cleared otherwise
– V - Set if an overflow occurs. Cleared otherwise
– C - Set if borrow occurs. Cleared otherwise
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: CMP.W D1, D0

D0 – D1 X N Z V C
D0 01 20 30 40 D1 01 20 30 40 0000 0 0 1 0 0

D0 01 30 30 41 D1 01 20 30 40 0001 0 0 0 0 0

D0 01 20 30 40 D1 01 20 30 41 FFFF 0 1 0 0 1

D0 01 20 FF FF D1 01 20 00 00 FFFF 0 1 0 0 0

D0 01 20 10 00 D1 01 20 20 00 F000 0 1 0 0 1

D0 01 20 70 00 D1 01 20 90 00 E000 0 1 0 1 1

D0 01 20 90 00 D1 01 20 70 00 2000 0 0 0 1 0
 THE 68000’S INSTRUCTION
SET (CONT..)
• Logical Instruction
A B AB AB AB A B
0 0 0 0 0 1 1
0 1 0 1 1 1 0
1 0 0 1 1 0 1
1 1 1 1 0 0 0

There are four types implementation for logical operation in MC68000

AND.s <sea>, <dea> either one is Dn operand

ANDI.s #data, <dea> source is immediate operand
OR.s <sea>, <dea> either one is Dn operand
ORI.s #data, <dea> source is immediate operand
EOR.s <sea>, <dea> either one is Dn operand
EORI.s #data, <dea> source is immediate operand
NOT.s <ea>
 THE 68000’S INSTRUCTION
SET (CONT..)
• AND instruction
– Used to clear more than 1 bit in operand
Example: To clear the entire bit except bit 0 – 3 in D0
Solution: ANDI.L #0F, D0

if D0 contains $0000B2DA

D0 0000 0000 0000 0000 1011 0010 1101 1010

#$0F 0000 0000 0000 0000 0000 0000 0000 1111
AND 0000 0000 0000 0000 0000 0000 0000 1010

Content of D0 after instruction: $0000000A

 THE 68000’S INSTRUCTION
SET (CONT..)
• OR instruction
– Used to set more than 1 bit in operand
Example: To set bit 5 – 7 in D0
Solution: ORI.W #00E0, D0

if D0 contains $A22D

D0 1010 0010 0010 1101

#$E0 0000 0000 1110 0000
OR 0000 0000 1110 1101

Content of D0 after instruction: $2AED

 THE 68000’S INSTRUCTION
SET (CONT..)
• EOR instruction
– Used to invert more than 1 bit in operand
Example: invert the lower word in D0
Solution: EORI.W #00FF, D0

if D0 contains $A22D

D0 1010 0010 0010 1101

#$FF 0000 0000 1111 1111
OR 0000 0000 1101 0010

Content of D0 after instruction: $2AD2

 THE 68000’S INSTRUCTION
SET (CONT..)
• NOT instruction
– Used to get the 1’s complement for the operand
Example: get the 1’s complement of lower byte in D0
Solution: NOT.B D0

if D0 contains $A22D

D0 1010 0010 0010 1101

NOT 0000 0000 1101 0010

Content of D0 after instruction: $2AD2

 THE 68000’S INSTRUCTION
SET (CONT..)
• Shift instruction
– There are 4 instructions for performing shift
operations
• ASL - arithmetic shift left
• ASR - arithmetic shift right
• LSL - logical shift left
• LSR - logical shift right

– Size = B, W, L
– Flag affected:
• X, C = depend to the bit shifted out
• N, Z = depend to the product
• V = 1 if shift operation changed the sign of operand
 THE 68000’S INSTRUCTION
SET (CONT..)
• Arithmetic Shift Instruction (Size = B, W, L)
– Arithmetically shift the bits of the operand in the direction
specified (L or R). The carry bit receives the last bit shifted out of
the operand. This shift count for the shifting of a register is
specified in two different ways:
• Immediate – The shift count (1-8) is specified in the instruction
• Register – The shift count is the value in the data register specified
in the instruction modulo 64

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
C 0 C

X X
ASL.B ASR.B
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: #2, D1
ASR.B
D1 12 34 56 F0 D1 12 34 56 FC

7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 0 0 C
Shift 1x
0 X
7 6 5 4 3 2 1 0
1 1 1 1 1 1 0 0 0 C
Shift 2x
0 X
 THE 68000’S INSTRUCTION
SET (CONT..)
• Logical Shift Instruction (Size = B, W, L)
– Shift the bits of the operand in the direction specified (L or R).
The carry bit receives the last bit shifted out of the operand. This
shift count for the shifting of a register is specified in two different
ways:
• Immediate – The shift count (1-8) is specified in the instruction
• Register – The shift count is the value in the data register specified
in the instruction modulo 64

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
C 0 0 C

X X
LSL.B LSR.B
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: #2, D1
LSR.B
D1 12 34 56 F0 D1 12 34 56 3C

7 6 5 4 3 2 1 0
0 0 1 1 1 1 0 0 0 0 C
Shift 1x
0 X
7 6 5 4 3 2 1 0
0 0 0 1 1 1 1 0 0 0 C
Shift 2x
0 X
 THE 68000’S INSTRUCTION
SET (CONT..)
• Rotate instruction
– Perform circular shift operations
– There are 4 instructions for performing shift operations
• ROL - rotate left
• ROR - rotate right
• ROXL - rotate left through X flag
• ROXR - rotate right through X flag

– Size = B, W, L
– Flag affected:
• X, C = depend to the bit shifted out
• N, Z = depend to the product
• V = 1 if the operation changed the sign of operand
 THE 68000’S INSTRUCTION
SET (CONT..)
• Rotate Instruction (Size = B, W, L)
– Rotate the bits of the operand in the direction specified (L or R).
The extend bit is not included in the rotation. The rotate count for
the rotation of a register is specified in either two ways:
• Immediate – The shift count (1-8) is specified in the instruction
• Register – The shift count is the value in the data register specified
in the instruction modulo 64

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
C C

ROL.B ROR.B
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: ROR.B #2,
D1
D1 12 34 56 A1 D1 12 34 56 68

7 6 5 4 3 2 1 0 C
1 1 0 1 0 0 0 0 1 Rotate 1x

7 6 5 4 3 2 1 0 C
0 1 1 0 1 0 0 0 0 Rotate 2x
 THE 68000’S INSTRUCTION
SET (CONT..)
• Rotate Instruction through X flag (Size = B, W, L)
– The ROXL and ROXR instruction perform rotate
instruction through the X flag

7 6 5 4 3 2 1 0 ROL.B
C X

7 6 5 4 3 2 1 0 ROR.B
X C
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example: ROXR.B #2,
D1
D1 12 34 56 A1 D1 12 34 56 A8

7 6 5 4 3 2 1 0 C
1 0 1 0 1 0 0 0 0 1 Rotate 1x

7 6 5 4 3 2 1 0 C
0 1 0 1 0 1 0 0 0 0 Rotate 2x

Given initial X = 0
 THE 68000’S INSTRUCTION
SET (CONT..)
• Bit manipulation instruction
– Test the specified bit in the destination by copying the
complement of that bit to the Z flag, which can then be checked
with a following conditional branch instruction
– Data size = B or 1 bit
– The bit manipulation instruction included:
• BCHG – bit test and change
• BCLR – bit test and clear
• BSET – bit test and set
• BTST – bit test
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 1:
– Address $FF8000 contains $AA. What is the result after BTST.B
#3, $FF8000
• Solution:
– The binary value in $FF8000 is 10101010 where the 3rd bit is 1.
After BTST.B #3, $FF8000, z bit will clear to 0 because 3rd bit in
$FF8000 is not 0.
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 2:
– Data register D5 contains 2C3459A7. What is the state of the Z
flag and what are the contents of D5 after BCHG #6,D5
executes?

• Solution:
– The binary representation of the lower byte of D5 is 10100111.
Bit 6, 1<0>100111, is a 0. This will cause the Z flag to be set and
the final state of bit 6 to be a 1. This will result in D5 containing
2C3459E7 once bit 6 is complemented.
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 3:
– Data registers D6 and D7 contain 0000000C and 75793290,
respectively. What is the result of BCLR D6,D7?

• Solution:
– Register D6 specifies that the 12th bit position should
be tested and cleared. The lower 16 bits of D7 with the
12th bit position indicated, are:
001<1>001010010000. Since this bit is a 1, the Z flag
will be cleared. Then bit 12 of D7 will be cleared,
resulting in a final value of 75792290.
 THE 68000’S INSTRUCTION
SET (CONT..)
• Program control instruction
– Jump instruction – JMP
– Jump instruction causes an unconditional transfer to
the target location.
– Program execution continues at the effective address
specified by the instruction.
– PC effective address
– Example: JMP START ;START =
$1000 JMP $2000
 THE 68000’S INSTRUCTION
SET (CONT..)
• Program control instruction
– Branch always instruction – BRA
– This is unconditional instruction
– BRA directly affects the processor’s program counter
with execution continuing at the address specified in
the instruction.
– PC PC + d
– Example: BRA START; START = $1000
 THE 68000’S INSTRUCTION
SET (CONT..)
• The Bcc instruction
– A Bcc (branch conditionally) has the
form Bcc <ea>
– cc represents the condition to be tested
– If the test condition is true, control is
transferred to the destination
– Otherwise, the next instruction following the conditional branch is
executed
THE 68000’S INSTRUCTION
SET (CONT..)
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 1: Compare two unsigned byte value located in memory.
The first byte is located in $2000, and the second byte is located in
$2001. Store the bigger value in address location $2002.

• Solution:
MOVE.B $2000, D0
CMP.B $2001, D0
BHS STORE
MOVE.B $2001, D0
STORE D0,
MOVE.B $2002
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 2: Change the ASCII value in lower byte of D2 to uppercase
if that byte contains lowercase.

• Solution:
CMP.B # ‘a’, D2
BCS FINISH
CMP.B # ‘z’, D2
BHI FINISH
SUB.B #$20, D2
FINISH END
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 3: Clear lower byte in D1 if lower word in D0 = 00, fill in D1
with -1 if D0  00. Then, store D1 in address location $2000

• Solution:
TST D0
BEQ ZERO
N_ZERO MOVE.Q # -1, D1
BRA FINISH
ZERO MOVEQ #0, D1
FINISH MOVE.B D1, $2000
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 4: Change the ASCII value in lower byte of D0 to the
equivalent hexadecimal value and store in lower byte of D1. If D0
does not contain ASCII number, fill in D1 with -1. Assume that there
are no lowercase in D0.
 THE 68000’S INSTRUCTION
SET (CONT..)
CMP.B # ’0’, D0 ;check with lower boundary
BCS ERROR ;if < 0 then error
CMP.B # ‘9’, D0 ;check with 2nd boundary
BHI CHECK2 ;if > 9, may be A – F
DIGIT SUB.B #$30, D0 ;Digit 0 – 9, so minus $30
BRA FINISH
CHECK2 CMP.B # ‘A’, D0
BCS.B ERROR ;if < ‘A’ then error
CMP.B #$ ‘F’, D0
BHI ERROR ;if > ‘F’ then error
SUB.B #$37, D0 ;Digit A – F, so minus $37
BRA FINISH
ERROR MOVEQ # -1, D0
FINISH MOVE.B D0, D1
 THE 68000’S INSTRUCTION
SET (CONT..)
• Example 5: Program below summed 5 16-bit integer located in
address $1000 through $1008

CLR.W D0 ;clear result

MOVEQ.B #5, D1 ;counter = 5
MOVEA.L #$1000, A0 ;initial (A0) pointer is location $1000
LOOP ADD.W (A0)+, D0 ;add word
SUBQ.B #1, D1 ;decrement counter
BNE LOOP ;if counter not zero, go to loop