BASIC PROCESSING UNIT

Some
Fundamental
Concepts
 Fundamental
Concepts
 Processor fetches one instruction at a time and performs the
operation specified.
 Instructions are fetched from successive memory locations
until a
branch or a jump instruction is encountered.
 The processor keeps track of the address of the memory location
containing the next instruction to be fetched using the Program
Counter (PC).
 After fetching an instruction, the contents of the PC are updated to
point to the next instruction in the sequence.
 A branch instruction may load a different value into the PC.
 Steps in Executing
an Instruction
 Fetch the contents of the memory location pointed to
by the PC. The contents of this location are loaded into
the instruction register IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte
addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
 Carry out the actions specified by the instruction in
the IR (execution phase).
Processor
Organization Control signals
 Processor
Organization..
 Figure shows an organization in which the ALU and all the registers are
interconnected via a single common bus.
 This bus is internal to the processor.
 The data and address lines of the external memory bus are connected to the
internal processor bus via the memory data register, MDR, and the memory
address register, MAR, respectively.
 Register MDR has two inputs and two outputs.
 Processor
Organization..
 Data may be loaded into MDR either from the memory bus or from
the internal processor bus.
 The data stored in MDR may be placed on either bus.
 The input of MAR is connected to the internal bus, and its output is
connected to the external bus.
 The control lines of the memory bus are connected to the instruction
decoder and control logic block.
 This unit is responsible for issuing the signals that control the

operation of all the units inside the processor and for interacting with
the memory bus.
 Processor
 Organization..
The number and use of the processor registers R0 through R(n - 1)
vary considerably from one processor to another.
 Registers may be provided for general-purpose use by
the programmer.
 Some may be dedicated as special-purpose registers, such as index

registers or stack pointers.

 The registers, Y, Z, and TEMP are used by the processor
for temporary storage during the execution of some instructions.
 These registers are never used for storing data generated

by one instruction for later use by another instruction.

 Processor
Organization..
 The multiplexer MUX selects either the output of register Y or a
constant value 4 to be provided as input A of the ALU.
 The constant 4 is used to increment the contents of the

program counter.
 We will refer to the two possible values of the MUX control input
Select as Select4 and SelectY for selecting the constant 4 or
register Y, respectively.
 Processor
 As Organization..
instruction execution progresses, data are transferred from one
register to another, often passing through the ALU to perform some
arithmetic or logic operation.
 The instruction decoder and control logic unit are responsible for
implementing the actions specified by the instruction loaded in the IR
register.
 The decoder generates the control signals needed to select the
registers
involved and direct the transfer of data.
 The registers, the ALU, and the interconnecting bus are
collectively
referred to as the datapath.
 Sequence of Steps in
Executing an
Instruction
 Transfer a word of data from one processor register to another or to
the
ALU.
 Perform an arithmetic or a logic operation and store the result
in a processor register.
 Fetch the contents of a given memory location and load them into a
processor register.
 Store a word of data from a processor register into a given memory
location.
 Register
Transfers
 Instruction execution involves a sequence of steps in which data
are transferred from one register to another.
 For each register, two control signals are used to place the contents of that register
on the bus or to load the data on the bus into the register.
 This is represented symbolically in Figure 7.2.
 The input and output of register Ri are connected to the bus via switches
controlled by the signals Riin and Riout respectively.
 When Riin is set to 1, the data on the bus are loaded into Ri.
 Similarly, when Riout is set to 1, the contents of register Ri are placed on the bus.
 While Rioutis equal to 0, the bus can be used for transferring data from other
registers.
Register Internal processor

Transfers.. R iin
bus

Ri

R iout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Register
Transfers..
 Register
Transfers..
 Suppose that we wish to transfer the contents of register
R1 to register R4.
 This can be accomplished as follows:
 Enable the output of register R1 by setting R1out to 1.
This places the contents of R1 on the processor bus.
 Enable the input of register R4 by setting R4in to 1.
This loads data from the processor bus into register R4.
 All operations and data transfers within the processor
take place within time periods defined by the processor
clock.
 Performing an
Arithmetic or Logic
Operation
 The ALU is a combinational circuit that has no internal storage.
 It performs arithmetic and logic operations on the two operands

applied to its A and B inputs.

 ALU gets the two operands from MUX and bus. The result is
temporarily stored in register Z.
 The sequence of operations to add the contents of register R1 to those of
R2 and store the result in R3.

1
. R1out, Yin
2. R2out, SelectY, Add,
Z
3 in
. Zout, R3in
 Performing an
Arithmetic or Logic
Operation..
 The signals whose names are given in any step are activated for
the duration of the clock cycle corresponding to that step.
 All other signals are inactive.

 In step 1, the output of register R1 and the input of register Y

are enabled, causing the contents of RI to be transferred over
the bus to Y.
 In step 2, the multiplexer's Select signal is set to SelectY,
causing the multiplexer to gate the contents of register Y
to input A of the ALU.
 In step 3, the contents of register Z are
transferred to the
destination register, R3.
 Fetching a Word
from Memory
 To fetch a word of information from memory, the processor has to
specify the address of the memory location where this
information is stored and request a Read operation.
 The information to be fetched may be an instruction in a program
or an operand specified by an instruction.
 The processor transfers the required address to the MAR, whose
output is connected to the address lines of the memory bus.
 At the same time, the processor uses the control lines of the
memory bus to indicate that a Read operation is needed.
 When the requested data are received from the memory they are
stored in register MDR,
 From MDR, they can be transferred to other registers in the
processor
Fetching a Word
from Memory..

Memory-bus
datalines Internal processor
bus
MDRout
MDRoutE

MDR

MDRinE

MDRin

Connection and control signals for register MDR.

 Fetching a Word
from Memory..
 Consider the instruction Move (R1), R2
 The actions needed to execute this

instruction are:
1. MAR ← [R1]

2. Start a Read operation on the memory bus

3. Wait for the MFC response from the

memory
4. Load MDR from the memory bus

5. R2 ← [MDR]
Fetching a Word
from Memory..
 The memory read operation requires
three steps, which can be described
by the signals being activated as
follows:
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in
 Storing a Word in
Memory
 The desired address is loaded into MAR.
 The data to be written are loaded into MDR and a Write command is
issued.
 Executing the instruction Move R2,(R1) requires the following
sequence:
1. R1out, MARin
2. R2out, MDRin, Write
3. MDRoutE,WMFC
 Execution of a
Complete Instruction
 Consider the instructionAdd (R3), R1
 Executing this instruction requires the following actions:
1. Fetch the instruction
2. Fetch the first operand (the contents of the memory location pointed to
by
R3)
3. Perform the addition
4. Load the result into R1
Execution of a Complete
Instruction.
Add (R3),
R1
Execution of
Branch
Instructions..
Multiple-Bus
Organization..
Multiple-Bus
Organization..
Consider the three-operand instruction Add R4,
R5, R6
 Multiple-Bus
Organization..
 In step 1, the contents of the PC are passed through the ALU, using the
R=B control signal, and loaded into the MAR to start a memory read
operation.
 At the same time the PC is incremented by 4.

 In step 2, the processor waits for MFC and loads the data
received into
MDR, then transfers them to IR in step 3.
 Finally, the execution phase of the instruction requires only one control
step to complete, step 4.
Hardwired
Control
Overvie
w
 To execute instructions, the
processor must have some means of
generating the control signals
needed in the proper sequence.
 Two categories:
 Hardwired control
 Microprogrammed control
 Hardwired system can operate at high
speed; but with little flexibility.
Hardwired Control –
Control Unit
Organization
 Consider the sequence of control
signals
given in Figure 7.6.
 Each step in this sequence is

completed in
one clock period.
 A counter may be used to keep track

of the
control steps, as shown in Figure
7.10.
Control Unit
Organization - Detailed
Block Description
Control Unit
Organization..
 The required control signals are
determined
by the following information:
 Contents of the control step counter
 Contents of the instruction register
 Contents of the condition code flags
 External input signals, such as MFC and
interrupt
requests
Generating
Zin
Zin = T1 + T6 • ADD + T4 •
BR + …

This signal is asserted

during time slot T1 for
all instructions,
during T6 for an Add
instruction, during T4
for an unconditional
branch instruction,
and so on.
A
Complete
Processor
A Complete
Processor
Instruction Integer Floating-
unit unit point
unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processo.

Microprogramm
ed Control
Overvie
w
 Control signals are generated by a
program
similar to machine language programs.
 A control word (CW) is a word whose

individual
bits represent the various control signals.
 A sequence of CWs corresponding to the

control sequence of a machine

instruction constitutes the microroutine for
that instruction.
 The individual control words in this
Microprogrammed
Control..

MDR out
icro -

WMFC
MAR in

Select
PC out

Read
instructi

R1out

R3out

End
Add
PC in

R1 in
Z out
IR in
Y in

Zin
o n
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An e xample of microinstructions for Figure

7.6.
Microprogrammed
Control..
Microprogrammed
Control..
Microprogrammed
Control..
 The previous organization cannot handle the situation
when the control unit is required to check the status of
the condition codes or external inputs to choose between
alternative courses of action.
 Can be handled by using conditional branch microinstruction.
 Interleaving

 Divides the memory system into a number of memory modules.

Each module has its own address buffer register (ABR) and data buffer register (DBR).
 Arranges addressing so that successive words in the address space
are placed in different modules.
 When requests for memory access involve consecutive addresses,
the access will be to different modules.
 Since parallel access to these modules is possible, the average
rate of fetching words from the Main Memory can be increased.
 Methods of address layouts

k bits m bits m bits k bits

Module Address in module MM address Address in module Module MM address

ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR ABR DBR

Module Module Module

Module Module Module k
0 i 2 - 1
0 i n- 1

 Consecutive words are placed in a •Consecutive words are located in

module. consecutive modules.
 High-order k bits of a memory address •Consecutive addresses can be located in
determine the module. consecutive modules.
 Low-order m bits of a memory address •While transferring a block of data,
determine the word within a module. several memory modules can be kept busy
 When a block of words is transferred at the same time.
from main memory to cache, only one
module is busy at a time.