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![CS211 17
Pipeline Performance: Speedup & Efficiency
k-stage pipeline processes n tasks in k + (n-1) clock
cycles:
k cycles for the first task and n-1 cycles
for the remaining n-1 tasks
Total time to process n tasks
Tk = [ k + (n-1)]
For the non-pipelined processor
T1 = n k
Speedup factor
Sk =
T1
Tk
=
n k
[ k + (n-1)]
=
n k
k + (n-1)
7](https://image.slidesharecdn.com/caopresentationpipelining-161213185856/85/Instruction-pipeline-Computer-Architecture-17-320.jpg)
![CS211 17
Pipeline Performance: Speedup & Efficiency
k-stage pipeline processes n tasks in k + (n-1) clock
cycles:
k cycles for the first task and n-1 cycles
for the remaining n-1 tasks
Total time to process n tasks
Tk = [ k + (n-1)]
For the non-pipelined processor
T1 = n k
Speedup factor
Sk =
T1
Tk
=
n k
[ k + (n-1)]
=
n k
k + (n-1)
7](https://image.slidesharecdn.com/caopresentationpipelining-161213185856/75/Instruction-pipeline-Computer-Architecture-17-2048.jpg)
Uploaded byInteX Research Lab
Instruction pipeline: Computer Architecture
Pipelining is a technique that allows multiple instructions to be executed in overlapping stages, improving efficiency, similar to processing laundry in stages. Each instruction undergoes fetching, decoding, executing, and memory operations in a structured pipeline, which can lead to significant time savings compared to non-pipelined execution. However, there are potential hazards such as structural, data, and control hazards that must be managed to maintain performance.
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Similar to Instruction pipeline: Computer Architecture
Instruction pipeline: Computer Architecture
- 1.
- 2. • A Pipeliningis a series of stages, where some work is done at each stage in parallel. • The stages are connected one to the next to form a pipe - instructions enter at one end, progress through the stages, and exit at the other end.
- 3. Pipelining Case: Laundry •4 loads of laundry that need to washed, dried, and folded. – 30 minutes to wash, 40 min. to dry, and 20 min. to fold. – We have 1 washer, 1 dryer, and 1 folding station. • What’s the most efficient way to get the 4 loads of laundry done?
- 4. Non Pipelined Laundry •Takes a total of 6 hours; nothing is done in parallel
- 5. Pipelined Laundry • Usingthis method, the laundry would be done at 9:30.
- 6. Definition: Pipelining is anspeed up technique where multiple instructions are overlapped in execution on a processor.
- 7. Pipelining: Processors • Computers,like laundry, typically perform the exact same steps for every instruction: – Fetch an instruction from memory – Decode the instruction – Execute the instruction – Read memory to get input – Write the result back to memory
- 8. CS211 8 Instruction Pipeline •Instruction execution process lends itself naturally to pipelining – overlap the subtasks of instruction fetch, decode and execute Fetch instruction (FI) Decode instruction (DI) Calculate operands (CO) Fetch operands (FO) Execute instructions (EI) Write result (WR) Overlap these operations • Instruction pipeline has six operations,
- 9. CS211 9 Instructions Fetch •The IF stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter are stored in the register as temporary storage.
- 10. CS211 10 Decode Instruction •The DI stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor.
- 11. CS211 11 Calculate Operands •The CO stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.
- 12. CS211 12 Fetch Operandsand Execute Instruction • The FO and EI stages are responsible for storing and loading values to and from memory. They also responsible for input and output from the processor respectively.
- 13. CS211 13 Write Operands •The WO stage is responsible for writing the result of a calculation, memory access or input into the register file.
- 14.
- 15. Timing Diagram for InstructionPipeline Operation
- 16. CS211 16 Pipeline Performance:Clock & Timing Si Si+1 m d Clock cycle of the pipeline : Latch delay : d = max {m } + d Pipeline frequency : f f = 1 / 6
- 17. CS211 17 Pipeline Performance:Speedup & Efficiency k-stage pipeline processes n tasks in k + (n-1) clock cycles: k cycles for the first task and n-1 cycles for the remaining n-1 tasks Total time to process n tasks Tk = [ k + (n-1)] For the non-pipelined processor T1 = n k Speedup factor Sk = T1 Tk = n k [ k + (n-1)] = n k k + (n-1) 7
- 18. Advantages • Pipelining makesefficient use of resources. • Quicker time of execution of large number of instructions • The parallelism is invisible to the programmer.
- 19. CSE431 L06 BasicMIPS Pipelining.19 Irwin, PSU, 2005 Yes: Pipeline Hazards structural hazards: attempt to use the same resource by two different instructions at the same time data hazards: attempt to use data before it is ready - An instruction’s source operand(s) are produced by a prior instruction still in the pipeline control hazards: attempt to make a decision about program control flow before the condition has been evaluated and the new PC target address calculated - branch instructions Can always resolve hazards by waiting pipeline control must detect the hazard and take action to resolve hazards Can Pipelining Get Us Into Trouble?
- 20.
- 21. Thank You!!! Md. SaidurRahman Kohinoor E-mail: mdsaidur.r.kohinoor@ieee.org Facebook: www.fb.com/kohinoor11