security in VLSI and challenges in VLSI cicuits

security in VLSI and challenges in VLSI cicuits

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  Security in VLSICircuits By K. Harsha Vardhini (249Y1D8407) Under the esteemed guidance of Dr. V. Vijaya Kishore Professor & HoD Department of ECE
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  Overview & Abstract •The Challenge: The proliferation of Very Large-Scale Integration (VLSI) circuits has introduced unprecedented security challenges that threaten the integrity, confidentiality, and availability of critical systems. • Threat Landscape: The multifaceted security landscape includes threats ranging from hardware Trojans and side-channel attacks to supply chain vulnerabilities. • Defense Mechanisms: This presentation explores state-of-the-art security measures like Physical Unclonable Functions (PUFs), Trusted Execution Environments (TEEs), secure boot mechanisms, and cryptographic hardware accelerators. • Objective: To contribute to the understanding of hardware security fundamentals and provide insights for developing robust security frameworks for next- generation VLSI systems
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  Introduction: Why VLSISecurity Matters • Ubiquitous Technology: VLSI circuits have revolutionized the electronics industry and form the backbone of modern computing systems. They are ubiquitous in our digital society, from smartphones to critical infrastructure. • Attractive Targets: This widespread adoption has made these circuits attractive targets for malicious actors seeking to exploit vulnerabilities. • Beyond Software: Traditional security approaches that focus on software are insufficient to address the unique challenges posed by hardware-level threats. • Evolving Threats: The globalized "fabless" design model and sophisticated attack techniques like differential power analysis (DPA) have intensified security concerns.
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  VLSI Security Fundamentals CoreObjectives (The CIA Triad): • Confidentiality: The protection of sensitive information from unauthorized access or disclosure, such as cryptographic keys. • Integrity: Ensures that the circuit functions as intended and has not been tampered with or modified by unauthorized parties. This is critical in the context of hardware Trojans. • Availability: Ensures that the circuit remains operational and accessible to authorized users , protecting against denial-of-service attacks or malicious logic
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  Threat 1: HardwareTrojans • What are they? Malicious modifications intentionally inserted into integrated circuits during the design or manufacturing process. • Classification: Trojans are categorized based on their: • Insertion Phase: Design-time, Manufacturing-time, Test-time, or Assembly-time . • Activation Mechanism: Can be always-on or conditionally-triggered by specific inputs or conditions. • Detection is Difficult: Trojans are challenging to detect due to their stealthy nature and the vast number of possible insertion methods. • Key Detection Methods: • Side-Channel Analysis: Exploits subtle changes in power consumption, timing, or electromagnetic emissions to detect Trojans. • Machine Learning: Approaches using algorithms like XGBoost have shown high accuracy in detecting Trojan-infected circuits.
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  Threat 2: Side-ChannelAttacks (SCA) • The Core Idea: Exploiting unintended information leakage from the physical implementation of cryptographic systems, rather than their mathematical properties. • Information Leakage: Variations in power consumption, timing, and electromagnetic emissions can be measured and analyzed to extract sensitive information like cryptographic keys. Types of SCA: • Power Analysis Attacks (SPA/DPA/CPA): Exploiting the relationship between a circuit's power consumption and the data it processes. • Timing Attacks: Exploiting variations in the execution time of cryptographic operations. • Electromagnetic (EM) Attacks: Exploiting electromagnetic emissions, which can be done without direct physical contact with the device.
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  Countermeasures for Side-Channel Attacks •Masking: Involves randomizing intermediate values in cryptographic computations to decorrelate power consumption from sensitive data. • Hiding: Aims to reduce the signal-to-noise ratio by making power consumption independent of the processed data. Techniques include power line filtering and noise injection. • Differential Logic Styles: Logic styles like Wave Dynamic Differential Logic (WDDL) are designed to consume constant power regardless of the data being processed. • Randomization: Introduces randomness into the execution of cryptographic operations, such as through random delays or random ordering of operations.
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  Solution 1: PhysicalUnclonable Functions (PUFs) • Hardware's "Fingerprint": PUFs leverage the inherent randomness of physical manufacturing processes to create secure identifiers and cryptographic keys. • Key Properties: • Uniqueness & Entropy: Critical properties that measure how different the responses are between PUF instances and quantify the amount of randomness. • Reliability & Stability: Important properties that ensure PUF responses remain consistent over time and across different environmental conditions. Core Applications: • Device Authentication: The unique challenge-response behavior serves as a digital fingerprint for device identification. • Secure Key Generation: Leverages the randomness of PUF responses to generate cryptographic keys without requiring external key storage.
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  Solution 2: TrustedExecution Environments (TEEs) • A Secure Enclave: TEEs provide isolated execution environments that protect sensitive code and data from potentially compromised system software and hardware. • Core Principle: Based on the concept of a reduced Trusted Computing Base (TCB), which minimizes the attack surface. Key Features: • Isolation Mechanisms: Provide both memory isolation and execution isolation between trusted and untrusted code. • Attestation: Enables a TEE to prove its identity and integrity to remote parties, establishing trust. • Examples: ARM TrustZone , Intel SGX (Software Guard Extensions) , and FPGA-based TEE solutions.
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  Solution 3: SecureBoot & Firmware Protection Goal: A critical security mechanism that ensures only authenticated and authorized firmware can be executed during system startup. The Chain of Trust: 1. Begins with an immutable 2. Root of Trust (RoT), typically code in read-only memory. 3. The RoT verifies the integrity and authenticity of the next stage bootloader. 4. Each subsequent component verifies the next, creating a continuous chain of verification. Key Mechanisms: • Cryptographic Verification: Typically involves digital signatures verified using public key cryptography. • Anti-Rollback Protection: Prevents adversaries from installing older, potentially vulnerable firmware versions.
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  Solution 4: CryptographicHardware Accelerators Purpose: Specialized processing units designed to perform cryptographic operations efficiently, providing significant performance improvements over software. Types of Accelerators: • Symmetric: AES accelerators are among the most commonly implemented. • Asymmetric: Accelerators for RSA and Elliptic Curve Cryptography (ECC). • Post-Quantum: Accelerators for quantum-resistant algorithms like lattice-based cryptography. • Security is Built-In: It's a critical requirement for accelerators to be resistant to side-channel attacks and fault injection attacks.
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  Supply Chain Security& Counterfeits The Problem: The globalization of semiconductor manufacturing has created a complex supply chain with numerous vulnerabilities that can be exploited by adversaries. Threats: • Counterfeit ICs: A major threat, including recycled, remarked, overproduced, or cloned parts that pose risks to system reliability and security. • Manufacturing Vulnerabilities: Can include the insertion of hardware Trojans or the compromise of the assembly and packaging process. Countermeasures: • Detection: Methods include physical inspection, X-ray inspection, and electrical testing. • Authentication: Using digital signatures or on-chip authentication mechanisms to verify authenticity. • Split Manufacturing: Can reduce risk by distributing the manufacturing process across multiple foundries so no single entity has the complete design
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  Emerging Security Challenges •Post-Quantum Cryptography (PQC): The advent of quantum computing poses an unprecedented threat to current cryptographic systems, necessitating the implementation of quantum-resistant algorithms in VLSI. • AI/ML Security: The deployment of AI accelerators has created new attack surfaces. • Attacks: Include extraction of proprietary models through side-channel analysis and adversarial attacks that cause misclassification. • IoT & Edge Security: The proliferation of IoT devices presents challenges due to resource constraints and deployment in hostile environments where physical access is possible.
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  Future Directions &Recommendations Research Priorities: • Developing efficient hardware implementations of • Quantum-Safe Cryptography. • Addressing both offensive and defensive aspects of • AI Security. • Developing comprehensive • Supply Chain Security solutions that address the entire lifecycle of components. Policy & Standards: • Update certification frameworks like Common Criteria and FIPS 140-2 to address emerging threats. • Strengthen • International Cooperation to address global security challenges like supply chain security. Industry Call to Action: • Increase • Investment in Security Research across the semiconductor industry. • Prioritize • Workforce Development to ensure adequate skilled personnel for VLSI security
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  Conclusion • Hardware isFoundational: Hardware security is foundational to overall system security, as vulnerabilities at this level can undermine all higher-level measures. • A Holistic Approach is Required: The challenges are multifaceted and require comprehensive solutions that span the entire lifecycle of integrated circuits. • Supply Chain is Critical: Supply chain security has emerged as a critical concern due to the globalized nature of semiconductor manufacturing. • Emerging Technologies Bring New Challenges: Technologies like post- quantum cryptography and AI are introducing new security challenges that must be carefully managed.
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  Thank You