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Uart VHDL RTL design tutorial | PPT
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Uart VHDL RTL design tutorial

The document discusses UART (Universal Asynchronous Receiver/Transmitter) and RS-232 communication standards. It describes the voltage levels used, the need for a converter chip between UART and RS-232, synchronous vs asynchronous transmission, baud rates, frame formats, and provides VHDL code for a UART transmitter and receiver implementation including state machines and registers.

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Overview of UART as Universal Asynchronous Receiver/Transmitter (UART) using logic levels of 0V and 5V for RS-232 signal levels.

Details on typical baud rates ranging from 75 to 330000. Discusses requirements including baud rate, stop bits, data bits, and parity.Description of RS-232 frame consisting of start bit, data bits, stop bit, and optional parity bit.

VHDL code for transmitter processes, including state machine, baud rate control, and shift register operations.

Presents simulation results of transmission and inferred memory devices in synthesis for the transmitter.

Receiver operation explanation, highlighting signal sampling, start bit detection, and use of counters.

VHDL code for receiver processes focusing on state management, data saving, and output processing.

Results of simulation and synthesis for the receiver, detailing register types, widths, and inferred components.

Details on area and power reports for the design, including total areas, dynamic power, and leakage power.

Proposed enhancements to UART with FIFO for data buffering, and features like independent registers and baud rate programming.

Description of testing FPGA functionality using PC interaction, demonstrating data transmission and reception.

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Nabil CHOUBA UART – RS-232 http:// nabil.chouba.googlepages.com
UART- RS-232 Universal Asynchronus Receiver/ Transmitter (UART) • The UART input/output uses 0V for logic 0 and 5V for logic 1. • RS232 signal levels : - logic 0 for signal between 3V and 25V - logic 1 for signal between -3V and -25V • To convert between these voltages levels we need an additional integrated circuit (such as Maxim’s MAX232).
TTL 0/5 to RS-232 -12/12
Asynchronous vs. Synchronous Asynchronous - Receiver and transmitter have separate clocks, running at the same nominal frequency - Synchronism achieved by detecting the start of each data word Synchronous - Receiver and transmitter synchronized by common clock (one clock to rule them all) - Much faster than asynchronous communications
RS-232 Pin Assignment
Baud Rate Typicall data rates: 75, 110, 300, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 33600, 56000, 115000 and (rarely) 330000 baud.
Transmission Re quirement Before transmission begins, transmitter and receiver must agree on : - Baut rate (75, 150, 300, 600, etc) - 1, 1.5 or 2 stop bits - 5, 6, 7 or 8 data bits - even, odd or no parity
RS-232 Frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 1 Every RS-232 Frame consists of: 1 start bit 8 data bits 1 stop bit (optional 1 parity bit) [a]= 0x61 = 0110 0001 P T tx = n .T clk T clk = 1/25 Mhz ,T tx = 1/9.6 Khz n = T tx /T clk , n = 25000/9.6
RTL View shift register b7 b6 b5 b4 b3 b2 b1 b0 run_shift load_shift Data_input shiftBit (start) ‘0’ (stop) ‘1’ parity xor xor xor xor xor xor xor parity Flip Flop tx State Machine seltx start Counter Bautrate bautrate run_brcount soft_rst_brcount 00 01 10 11
Transmitter Tx idle b_start b_0 b_6 b_1 b_5 b_4 b_3 b_2 b_parity b_stop start seltx <= '01'; run_brcount <= ‘1’; Load_shift <= ‘1’ run_brcount <= ‘1’; seltx <= ’11’; seltx <= '10'; soft_count_rst <= ‘1’ seltx <='10'; run_brcount <= ‘1’; rst bautrate run_brcount <= ‘1’; seltx <= ‘00’ run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; bautrate bautrate bautrate b_7 run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1'
VHDL CODE cloked_process : process( clk, rst ) begin if( rst='1' ) then state_reg <= idle ; counter_bautrate_reg <= (others =>'0') ; data_shift_reg <= (others =>'0') ; elsif( clk'event and clk='1' ) then state_reg<= state_next ; counter_bautrate_reg <= counter_bautrate_next; data_shift_reg <= data_shift_next; end if; end process ; bautrate <= '1' when counter_bautrate_reg = 5200 else '0'; BR_COUNTER : process( counter_bautrate_reg, run_brcount, soft_rst_brcount,bautrate ) begin counter_bautrate_next <= counter_bautrate_reg; if soft_rst_brcount = '1' or bautrate = '1' then counter_bautrate_next <= (others=>'0'); elsif( run_brcount = '1' ) then counter_bautrate_next <= counter_bautrate_reg + 1 ; end if ; end process ; comb_shift:process (load_shift,data_shift_reg,run_shift,data,bautrate) begin data_shift_next<= data_shift_reg; if load_shift ='1' then data_shift_next <=data; elsif run_shift ='1' and bautrate = '1' then data_shift_next <= data_shift_reg(0) & data_shift_reg(7 downto 1); end if; end process; shiftBit <= data_shift_reg(0); parity<=data_shift_reg(0)xor data_shift_reg(1)xor data_shift_reg(2)xor data_shift_reg(3)xor data_shift_reg(4)xor data_shift_reg(5)xor data_shift_reg(6)xor data_shift_reg(7); tx <= shiftBit when seltx =&quot;00&quot; else -- Data bit '0' when seltx =&quot;01&quot; else -- Start bit '1' when seltx =&quot;01&quot; else -- Stop bit parity ;
VHDL CODE --next state processing combinatory_FSM_next : process(state_reg,start,bautrate) begin state_next<= state_reg; case state_reg is when idle => if start = '1' then state_next <= b_start; end if; when b_start => if bautrate = '1' then state_next <= b_0; end if; when b_0 => if bautrate = '1' then state_next <= b_1; end if; when b_6 => if bautrate = '1' then state_next <= b_7; end if; when b_7 => if bautrate = '1' then state_next <= b_parity; end if; when b_parity => if bautrate = '1' then state_next <= b_stop; end if; when b_stop => if bautrate = '1' then state_next <= idle; end if; when others => end case; end process; when b_1 => if bautrate = '1' then state_next <= b_2; end if; when b_2 => if bautrate = '1' then state_next <= b_3; end if; when b_3 => if bautrate = '1' then state_next <= b_4; end if; when b_4 => if bautrate = '1' then state_next <= b_5; end if; when b_5 => if bautrate = '1' then state_next <= b_6; end if;
VHDL CODE --controls output processing combinatory_output : process(state_reg ) begin run_brcount <= '0'; seltx <= &quot;10&quot;; --stop bit; soft_rst_brcount <= '0'; Load_shift <= '0'; run_shift <= '0'; case state_reg is when idle => seltx <= &quot;10&quot;; --stop bit; soft_rst_brcount <= '0'; when b_start => seltx <= &quot;01&quot;; run_brcount <= '1'; Load_shift <= '1'; when b_0 | b_1 b_2 | b_3 |b_4 | b_5 |b_6 | b_7 => run_brcount <= '1'; run_shift <= '1'; seltx <= &quot;00&quot;; when b_parity => run_brcount <= '1'; seltx <= &quot;11&quot;; when b_stop => seltx <=&quot;10&quot;; run_brcount <= '1'; when others => end case; end process;
Simulation Result (Mentor vsim) Sending [ 0xC1 ] = 1100 0001
Synthesis Result (designvision / synopsys) Inferred memory devices in process in routine transmiter line 61 in file '/home/chouban/tp_vhdl/rs232/transmiter.vhd'. =================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =================================================================== | data_shift_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | | state_reg_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | | counter_bautrate_reg_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | ===================================================================
Synthesis Result (designvision / synopsys/ GTEC Library ) State register bautrate generation Shift register Next State FSM output Mux seltx
Mux – seltx (designvision / synopsys)
Shift register (designvision / synopsys)
bautrate generation (designvision / synopsys)
FSM output (designvision / synopsys)
state : register & next (designvision / synopsys)
Receiver sampling signal Start bit bit 0 bit 1 bit 2 8 16 16 16 The receiver uses the falling edge of the start bit to begin an internal timing circuit. We use generally 16x the Bautrate to sample the received signal. - The data should be most stable, approximately at the mid-position of each data bit.
RTL View shift register b7 b6 b5 b4 b3 b2 b1 b0 run_shift save_data Data_output State Machine Counter Bautrate run_brcount soft_rst_brcount b7 b6 b5 b4 b3 b2 b1 b0 bautrate8 rx Detect Start Bit detect_start Data_ready
Receiver Rx b_start b_0 b_6 b_1 b_5 b_4 b_3 b_2 b_7 b_stop soft_rst_brcount <=‘1’ Bautrate8 idle detect_start parity run_brcount <= ‘1’ run_brcount <= ‘1’ Bautrate8 / run_shift <='1'; run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 Bautrate8 / save_data <='1'; data_ready <= '1';
VHDL CODE cloked_process : process( clk, rst ) begin if( rst='1' ) then state_reg <= idle ; counter_bautrate_reg <= (others =>'0') ; data_shift_reg <= (others =>'0') ; data_save_reg <= (others =>'0') ; rx_reg <= '0'; elsif( clk'event and clk='1' ) then state_reg<= state_next ; counter_bautrate_reg <= counter_bautrate_next; data_shift_reg <= data_shift_next; data_save_reg <= data_save_next ; rx_reg <= rx_next; end if; end process ; bautrate16 <= '1' when counter_bautrate_reg = 5200 else '0'; bautrate8 <= '1' when counter_bautrate_reg = 2600 else '0'; BR_COUNTER_GEN : process( counter_bautrate_reg, run_brcount, soft_rst_brcount, bautrate16 ) begin counter_bautrate_next <= counter_bautrate_reg; if soft_rst_brcount = '1' or bautrate16 = '1' then counter_bautrate_next <= (others=>'0'); elsif( run_brcount = '1' ) then counter_bautrate_next <= counter_bautrate_reg + 1 ; end if ; end process ;
VHDL CODE comb_shift:process(data_shift_reg,run_shift,rx) begin data_shift_next<= data_shift_reg; if run_shift ='1' then data_shift_next <= rx & data_shift_reg(7 downto 1); end if; end process; rx_next <= rx; detect_start <= '1' when rx_next = '0' and rx_reg = '1' else '0'; data_save_next <= data_shift_reg when save_data = '1' else data_save_reg; data <= data_save_reg;
VHDL CODE --next state processing combinatory_FSM_next : process(state_reg, detect_start, bautrate8, bautrate16) begin state_next<= state_reg; case state_reg is when idle => if detect_start = '1' then state_next <= b_start; end if; when b_start => if bautrate8 = '1' then state_next <= b_0; end if; when b_0 => if bautrate8 = '1' then state_next <= b_1; end if; when b_1 => if bautrate8 = '1' then state_next <= b_2; end if; when b_2 => if bautrate8 = '1' then state_next <= b_3; end if; when b_3 => if bautrate8 = '1' then state_next <= b_4; end if; when b_4 => if bautrate8 = '1' then state_next <= b_5; end if; when b_5 => if bautrate8 = '1' then state_next <= b_6; end if; when b_6 => if bautrate8 = '1' then state_next <= b_7; end if; when b_7 => if bautrate8 = '1' then state_next <= b_parity; end if; when b_parity => if bautrate8 = '1' then state_next <= b_stop; end if; when b_stop => if bautrate8 = '1' then state_next <= idle; end if; when others => end case; end process;
VHDL CODE --output processing combinatory_output : process(state_reg, detect_start, bautrate8, bautrate16) begin run_brcount <='0'; data_ready <= '0'; save_data <= '0'; soft_rst_brcount<='0'; run_shift <='0'; case state_reg is when idle => soft_rst_brcount<=‘1'; when b_start => run_brcount <='1'; when b_0 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_1 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_2 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_3 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_4 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_5 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_6 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_7 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_parity => run_brcount <='1'; when b_stop => run_brcount <='1'; if bautrate8 = '1' then save_data <= '1'; end if; when others => end case; end process;
Testbench clk <= not clk after 50 ns; rst <= '0' after 150 ns; tb : PROCESS BEGIN -- idle bit rx <= '1'; -- wiat wait for 100 * 5200 ns; --stat bit rx <= '0'; wait for 100 * 5200 ns; for i in 0 to 7 loop rx <= send_data(i); wait for 100 * 5200 ns; end loop; -- party bit not implemented rx <= '-'; wait for 100 * 5200 ns; -- stop bit rx <= '1'; wait for 100 * 5200 ns; -- do nothing wait for 100 * 5200 ns; -- test if rw data = to sended data assert (data = send_data) report &quot; data /= send_data&quot; severity Error; -- end of simulation wait for 1000ns; assert (2=1) report &quot;end simulation&quot; severity note; wait; -- will wait forever end process;
Simulation Result (Mentor vsim) Data resived : 10101010
Synthesis Result (design_vision / synopsys/cmos65 Library ) Inferred memory devices in process in routine resiver line 60 in file '/home/chouban/tp_vhdl/rs232/resiver.vhd'. ===================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | ===================================================================== | rx_reg_reg | Flip-flop | 1 | N | N | Y | N | N | N | N | | state_reg_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | | counter_bautrate_reg_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | | data_shift_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | | data_save_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | =====================================================================
Synthesis Result (design_vision / synopsys/ cmos65 ) save register shift register Counter Bautrate State Machin
Save data register & logic /cmos65
shift data register & logic /cmos65
State Machin /cmos65
Counter Bautrate /cmos65
Report : area (cmos65) **************************************** Report : area Design : resiver Version: Z-2007.03-SP5-1 Date : Wed May 6 12:20:00 2009 **************************************** Library(s) Used: CORE65 Number of ports: 12 Number of nets: 148 Number of cells: 130 Number of references: 23 Combinational area: 364.519990 Noncombinational area: 384.799986 Net Interconnect area: undefined (Wire load has zero net area) Total cell area: 749.319946 ***** End Of Report *****
Report : Power (cmos65) **************************************** Report : power -analysis_effort low Design : resiver Version: Z-2007.03-SP5-1 Date : Wed May 6 12:21:43 2009 **************************************** Global Operating Voltage = 1.1 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW Cell Internal Power = 1.2396 uW (77%) Net Switching Power = 367.3567 nW (23%) --------- Total Dynamic Power = 1.6070 uW (100%) Cell Leakage Power = 13.1999 uW
Report : reference eference Library Unit Area Count Total Area Attributes ----------------------------------------------------------------------------- HS65_LS_AND2X4 CORE65xxxx 2.600000 1 2.600000 HS65_LS_AO12X9 CORE65xxxx 3.640000 1 3.640000 HS65_LS_AO22X9 CORE65xxxx 4.160000 32 133.119995 HS65_LS_AOI22X6 CORE65xxxx 3.640000 1 3.640000 HS65_LS_AOI32X5 CORE65xxxx 4.160000 2 8.320000 HS65_LS_BFX9 CORE65xxxx 2.080000 3 6.240000 HS65_LS_CBI4I1X5 CORE65xxxx 3.640000 1 3.640000 HS65_LS_DFPRQNX9 CORE65xx 10.400000 12 124.799995 n HS65_LS_DFPRQX9 CORE65xxx 10.400000 25 259.999990 n HS65_LS_IVX9 CORE65xxxx 1.560000 20 31.199999 HS65_LS_NAND2AX7 CORE65xx 3.120000 1 3.120000 HS65_LS_NAND2X7 CORE65xxx 2.080000 2 4.160000 HS65_LS_NAND3X5 CORE65xxx 2.600000 3 7.800000 HS65_LS_NAND4ABX3 CORE65x 3.640000 2 7.280000 HS65_LS_NOR2X6 CORE65xxxx 2.080000 5 10.400000 HS65_LS_NOR3AX4 CORE65xxx 3.640000 1 3.640000 HS65_LS_NOR3X4 CORE65xxxx 2.600000 5 13.000000 HS65_LS_NOR4ABX2 CORE65xx 3.640000 6 21.840001 HS65_LS_OAI13X5 CORE65xxx 3.640000 1 3.640000 HS65_LS_OAI21X3 CORE65xxx 2.600000 2 5.200000 HS65_LS_OAI212X5 CORE65xxx 4.160000 2 8.320000 HS65_LS_OAI222X2 CORE65xxx 5.200000 1 5.200000 resiver_DW01_inc_0 78.519997 1 78.519997 h ----------------------------------------------------------------------------- Total 23 references 749.319976
UART : Enhancement add FIFO for : data received add FIFO for : data to transmit => Use of dual port ram (fifo_full/fifo_empty) programmable - Bautrate : 75, 150, 300, 600, etc - 1, 1.5 or 2 stop bits - 5, 6, 7 or 8 data bits - even, odd or no parity => Add configurable register, add command signal
Exemple of UART on µc 7- or 8-bit data with odd, even, or non-parity Independent transmit/receive shift registers Separate transmit and receive buffer registers LSB-first or MSB-first data transmit and receive Receiver start-edge detection for auto-wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression Independent interrupt capability for receive and transmit * TI / MSP430
FPGA over-all Test When buttons is pushed , PC receive : [a]= 0x61 PC send data to FPGA : data are displayed on leds => Use HyperTerminal to send and receive data receiver transmitter start debounce data=[a]= 0x61 tx rx Data_ready data PC PC

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Uart VHDL RTL design tutorial

  • 1.
    Nabil CHOUBA UART– RS-232 http:// nabil.chouba.googlepages.com
  • 2.
    UART- RS-232Universal Asynchronus Receiver/ Transmitter (UART) • The UART input/output uses 0V for logic 0 and 5V for logic 1. • RS232 signal levels : - logic 0 for signal between 3V and 25V - logic 1 for signal between -3V and -25V • To convert between these voltages levels we need an additional integrated circuit (such as Maxim’s MAX232).
  • 3.
    TTL 0/5 toRS-232 -12/12
  • 4.
    Asynchronous vs. SynchronousAsynchronous - Receiver and transmitter have separate clocks, running at the same nominal frequency - Synchronism achieved by detecting the start of each data word Synchronous - Receiver and transmitter synchronized by common clock (one clock to rule them all) - Much faster than asynchronous communications
  • 5.
    RS-232 Pin Assignment
  • 6.
    Baud Rate Typicalldata rates: 75, 110, 300, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 33600, 56000, 115000 and (rarely) 330000 baud.
  • 7.
    Transmission Re quirementBefore transmission begins, transmitter and receiver must agree on : - Baut rate (75, 150, 300, 600, etc) - 1, 1.5 or 2 stop bits - 5, 6, 7 or 8 data bits - even, odd or no parity
  • 8.
    RS-232 Frame StartD0 D1 D2 D3 D4 D5 D6 D7 Stop 1 1 1 1 0 1 0 0 0 0 1 1 0 0 1 1 Every RS-232 Frame consists of: 1 start bit 8 data bits 1 stop bit (optional 1 parity bit) [a]= 0x61 = 0110 0001 P T tx = n .T clk T clk = 1/25 Mhz ,T tx = 1/9.6 Khz n = T tx /T clk , n = 25000/9.6
  • 9.
    RTL View shiftregister b7 b6 b5 b4 b3 b2 b1 b0 run_shift load_shift Data_input shiftBit (start) ‘0’ (stop) ‘1’ parity xor xor xor xor xor xor xor parity Flip Flop tx State Machine seltx start Counter Bautrate bautrate run_brcount soft_rst_brcount 00 01 10 11
  • 10.
    Transmitter Tx idle b_start b_0 b_6 b_1 b_5 b_4 b_3 b_2 b_parity b_stop start seltx <= '01'; run_brcount <= ‘1’; Load_shift <= ‘1’ run_brcount <= ‘1’; seltx <= ’11’; seltx <= '10'; soft_count_rst <= ‘1’ seltx <='10'; run_brcount <= ‘1’; rst bautrate run_brcount <= ‘1’; seltx <= ‘00’ run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; bautrate bautrate bautrate b_7 run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; run_brcount <= ‘1’; seltx <=‘00’; Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1' Bautrate / run_shift <= '1'
  • 11.
    VHDL CODE cloked_process: process( clk, rst ) begin if( rst='1' ) then state_reg <= idle ; counter_bautrate_reg <= (others =>'0') ; data_shift_reg <= (others =>'0') ; elsif( clk'event and clk='1' ) then state_reg<= state_next ; counter_bautrate_reg <= counter_bautrate_next; data_shift_reg <= data_shift_next; end if; end process ; bautrate <= '1' when counter_bautrate_reg = 5200 else '0'; BR_COUNTER : process( counter_bautrate_reg, run_brcount, soft_rst_brcount,bautrate ) begin counter_bautrate_next <= counter_bautrate_reg; if soft_rst_brcount = '1' or bautrate = '1' then counter_bautrate_next <= (others=>'0'); elsif( run_brcount = '1' ) then counter_bautrate_next <= counter_bautrate_reg + 1 ; end if ; end process ; comb_shift:process (load_shift,data_shift_reg,run_shift,data,bautrate) begin data_shift_next<= data_shift_reg; if load_shift ='1' then data_shift_next <=data; elsif run_shift ='1' and bautrate = '1' then data_shift_next <= data_shift_reg(0) & data_shift_reg(7 downto 1); end if; end process; shiftBit <= data_shift_reg(0); parity<=data_shift_reg(0)xor data_shift_reg(1)xor data_shift_reg(2)xor data_shift_reg(3)xor data_shift_reg(4)xor data_shift_reg(5)xor data_shift_reg(6)xor data_shift_reg(7); tx <= shiftBit when seltx =&quot;00&quot; else -- Data bit '0' when seltx =&quot;01&quot; else -- Start bit '1' when seltx =&quot;01&quot; else -- Stop bit parity ;
  • 12.
    VHDL CODE --nextstate processing combinatory_FSM_next : process(state_reg,start,bautrate) begin state_next<= state_reg; case state_reg is when idle => if start = '1' then state_next <= b_start; end if; when b_start => if bautrate = '1' then state_next <= b_0; end if; when b_0 => if bautrate = '1' then state_next <= b_1; end if; when b_6 => if bautrate = '1' then state_next <= b_7; end if; when b_7 => if bautrate = '1' then state_next <= b_parity; end if; when b_parity => if bautrate = '1' then state_next <= b_stop; end if; when b_stop => if bautrate = '1' then state_next <= idle; end if; when others => end case; end process; when b_1 => if bautrate = '1' then state_next <= b_2; end if; when b_2 => if bautrate = '1' then state_next <= b_3; end if; when b_3 => if bautrate = '1' then state_next <= b_4; end if; when b_4 => if bautrate = '1' then state_next <= b_5; end if; when b_5 => if bautrate = '1' then state_next <= b_6; end if;
  • 13.
    VHDL CODE --controlsoutput processing combinatory_output : process(state_reg ) begin run_brcount <= '0'; seltx <= &quot;10&quot;; --stop bit; soft_rst_brcount <= '0'; Load_shift <= '0'; run_shift <= '0'; case state_reg is when idle => seltx <= &quot;10&quot;; --stop bit; soft_rst_brcount <= '0'; when b_start => seltx <= &quot;01&quot;; run_brcount <= '1'; Load_shift <= '1'; when b_0 | b_1 b_2 | b_3 |b_4 | b_5 |b_6 | b_7 => run_brcount <= '1'; run_shift <= '1'; seltx <= &quot;00&quot;; when b_parity => run_brcount <= '1'; seltx <= &quot;11&quot;; when b_stop => seltx <=&quot;10&quot;; run_brcount <= '1'; when others => end case; end process;
  • 14.
    Simulation Result(Mentor vsim) Sending [ 0xC1 ] = 1100 0001
  • 15.
    Synthesis Result (designvision / synopsys) Inferred memory devices in process in routine transmiter line 61 in file '/home/chouban/tp_vhdl/rs232/transmiter.vhd'. =================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =================================================================== | data_shift_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | | state_reg_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | | counter_bautrate_reg_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | ===================================================================
  • 16.
    Synthesis Result (designvision / synopsys/ GTEC Library ) State register bautrate generation Shift register Next State FSM output Mux seltx
  • 17.
    Mux – seltx (designvision / synopsys)
  • 18.
    Shift register (designvision / synopsys)
  • 19.
    bautrate generation (designvision / synopsys)
  • 20.
    FSM output (designvision / synopsys)
  • 21.
    state : register& next (designvision / synopsys)
  • 22.
    Receiver sampling signal Start bit bit 0 bit 1 bit 2 8 16 16 16 The receiver uses the falling edge of the start bit to begin an internal timing circuit. We use generally 16x the Bautrate to sample the received signal. - The data should be most stable, approximately at the mid-position of each data bit.
  • 23.
    RTL View shiftregister b7 b6 b5 b4 b3 b2 b1 b0 run_shift save_data Data_output State Machine Counter Bautrate run_brcount soft_rst_brcount b7 b6 b5 b4 b3 b2 b1 b0 bautrate8 rx Detect Start Bit detect_start Data_ready
  • 24.
    Receiver Rxb_start b_0 b_6 b_1 b_5 b_4 b_3 b_2 b_7 b_stop soft_rst_brcount <=‘1’ Bautrate8 idle detect_start parity run_brcount <= ‘1’ run_brcount <= ‘1’ Bautrate8 / run_shift <='1'; run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ run_brcount <= ‘1’ Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 / run_shift <='1'; Bautrate8 Bautrate8 / save_data <='1'; data_ready <= '1';
  • 25.
    VHDL CODE cloked_process: process( clk, rst ) begin if( rst='1' ) then state_reg <= idle ; counter_bautrate_reg <= (others =>'0') ; data_shift_reg <= (others =>'0') ; data_save_reg <= (others =>'0') ; rx_reg <= '0'; elsif( clk'event and clk='1' ) then state_reg<= state_next ; counter_bautrate_reg <= counter_bautrate_next; data_shift_reg <= data_shift_next; data_save_reg <= data_save_next ; rx_reg <= rx_next; end if; end process ; bautrate16 <= '1' when counter_bautrate_reg = 5200 else '0'; bautrate8 <= '1' when counter_bautrate_reg = 2600 else '0'; BR_COUNTER_GEN : process( counter_bautrate_reg, run_brcount, soft_rst_brcount, bautrate16 ) begin counter_bautrate_next <= counter_bautrate_reg; if soft_rst_brcount = '1' or bautrate16 = '1' then counter_bautrate_next <= (others=>'0'); elsif( run_brcount = '1' ) then counter_bautrate_next <= counter_bautrate_reg + 1 ; end if ; end process ;
  • 26.
    VHDL CODE comb_shift:process(data_shift_reg,run_shift,rx)begin data_shift_next<= data_shift_reg; if run_shift ='1' then data_shift_next <= rx & data_shift_reg(7 downto 1); end if; end process; rx_next <= rx; detect_start <= '1' when rx_next = '0' and rx_reg = '1' else '0'; data_save_next <= data_shift_reg when save_data = '1' else data_save_reg; data <= data_save_reg;
  • 27.
    VHDL CODE --nextstate processing combinatory_FSM_next : process(state_reg, detect_start, bautrate8, bautrate16) begin state_next<= state_reg; case state_reg is when idle => if detect_start = '1' then state_next <= b_start; end if; when b_start => if bautrate8 = '1' then state_next <= b_0; end if; when b_0 => if bautrate8 = '1' then state_next <= b_1; end if; when b_1 => if bautrate8 = '1' then state_next <= b_2; end if; when b_2 => if bautrate8 = '1' then state_next <= b_3; end if; when b_3 => if bautrate8 = '1' then state_next <= b_4; end if; when b_4 => if bautrate8 = '1' then state_next <= b_5; end if; when b_5 => if bautrate8 = '1' then state_next <= b_6; end if; when b_6 => if bautrate8 = '1' then state_next <= b_7; end if; when b_7 => if bautrate8 = '1' then state_next <= b_parity; end if; when b_parity => if bautrate8 = '1' then state_next <= b_stop; end if; when b_stop => if bautrate8 = '1' then state_next <= idle; end if; when others => end case; end process;
  • 28.
    VHDL CODE --outputprocessing combinatory_output : process(state_reg, detect_start, bautrate8, bautrate16) begin run_brcount <='0'; data_ready <= '0'; save_data <= '0'; soft_rst_brcount<='0'; run_shift <='0'; case state_reg is when idle => soft_rst_brcount<=‘1'; when b_start => run_brcount <='1'; when b_0 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_1 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_2 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_3 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_4 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_5 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_6 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_7 => run_brcount <='1'; if bautrate8 = '1' then run_shift <='1'; end if; when b_parity => run_brcount <='1'; when b_stop => run_brcount <='1'; if bautrate8 = '1' then save_data <= '1'; end if; when others => end case; end process;
  • 29.
    Testbench clk <=not clk after 50 ns; rst <= '0' after 150 ns; tb : PROCESS BEGIN -- idle bit rx <= '1'; -- wiat wait for 100 * 5200 ns; --stat bit rx <= '0'; wait for 100 * 5200 ns; for i in 0 to 7 loop rx <= send_data(i); wait for 100 * 5200 ns; end loop; -- party bit not implemented rx <= '-'; wait for 100 * 5200 ns; -- stop bit rx <= '1'; wait for 100 * 5200 ns; -- do nothing wait for 100 * 5200 ns; -- test if rw data = to sended data assert (data = send_data) report &quot; data /= send_data&quot; severity Error; -- end of simulation wait for 1000ns; assert (2=1) report &quot;end simulation&quot; severity note; wait; -- will wait forever end process;
  • 30.
    Simulation Result(Mentor vsim) Data resived : 10101010
  • 31.
    Synthesis Result (design_vision / synopsys/cmos65 Library ) Inferred memory devices in process in routine resiver line 60 in file '/home/chouban/tp_vhdl/rs232/resiver.vhd'. ===================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | ===================================================================== | rx_reg_reg | Flip-flop | 1 | N | N | Y | N | N | N | N | | state_reg_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N | | counter_bautrate_reg_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | | data_shift_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | | data_save_reg_reg | Flip-flop | 8 | Y | N | Y | N | N | N | N | =====================================================================
  • 32.
    Synthesis Result (design_vision / synopsys/ cmos65 ) save register shift register Counter Bautrate State Machin
  • 33.
    Save data register& logic /cmos65
  • 34.
    shift data register& logic /cmos65
  • 35.
  • 36.
  • 37.
    Report : area(cmos65) **************************************** Report : area Design : resiver Version: Z-2007.03-SP5-1 Date : Wed May 6 12:20:00 2009 **************************************** Library(s) Used: CORE65 Number of ports: 12 Number of nets: 148 Number of cells: 130 Number of references: 23 Combinational area: 364.519990 Noncombinational area: 384.799986 Net Interconnect area: undefined (Wire load has zero net area) Total cell area: 749.319946 ***** End Of Report *****
  • 38.
    Report : Power(cmos65) **************************************** Report : power -analysis_effort low Design : resiver Version: Z-2007.03-SP5-1 Date : Wed May 6 12:21:43 2009 **************************************** Global Operating Voltage = 1.1 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW Cell Internal Power = 1.2396 uW (77%) Net Switching Power = 367.3567 nW (23%) --------- Total Dynamic Power = 1.6070 uW (100%) Cell Leakage Power = 13.1999 uW
  • 39.
    Report : referenceeference Library Unit Area Count Total Area Attributes ----------------------------------------------------------------------------- HS65_LS_AND2X4 CORE65xxxx 2.600000 1 2.600000 HS65_LS_AO12X9 CORE65xxxx 3.640000 1 3.640000 HS65_LS_AO22X9 CORE65xxxx 4.160000 32 133.119995 HS65_LS_AOI22X6 CORE65xxxx 3.640000 1 3.640000 HS65_LS_AOI32X5 CORE65xxxx 4.160000 2 8.320000 HS65_LS_BFX9 CORE65xxxx 2.080000 3 6.240000 HS65_LS_CBI4I1X5 CORE65xxxx 3.640000 1 3.640000 HS65_LS_DFPRQNX9 CORE65xx 10.400000 12 124.799995 n HS65_LS_DFPRQX9 CORE65xxx 10.400000 25 259.999990 n HS65_LS_IVX9 CORE65xxxx 1.560000 20 31.199999 HS65_LS_NAND2AX7 CORE65xx 3.120000 1 3.120000 HS65_LS_NAND2X7 CORE65xxx 2.080000 2 4.160000 HS65_LS_NAND3X5 CORE65xxx 2.600000 3 7.800000 HS65_LS_NAND4ABX3 CORE65x 3.640000 2 7.280000 HS65_LS_NOR2X6 CORE65xxxx 2.080000 5 10.400000 HS65_LS_NOR3AX4 CORE65xxx 3.640000 1 3.640000 HS65_LS_NOR3X4 CORE65xxxx 2.600000 5 13.000000 HS65_LS_NOR4ABX2 CORE65xx 3.640000 6 21.840001 HS65_LS_OAI13X5 CORE65xxx 3.640000 1 3.640000 HS65_LS_OAI21X3 CORE65xxx 2.600000 2 5.200000 HS65_LS_OAI212X5 CORE65xxx 4.160000 2 8.320000 HS65_LS_OAI222X2 CORE65xxx 5.200000 1 5.200000 resiver_DW01_inc_0 78.519997 1 78.519997 h ----------------------------------------------------------------------------- Total 23 references 749.319976
  • 40.
    UART : Enhancement add FIFO for : data received add FIFO for : data to transmit => Use of dual port ram (fifo_full/fifo_empty) programmable - Bautrate : 75, 150, 300, 600, etc - 1, 1.5 or 2 stop bits - 5, 6, 7 or 8 data bits - even, odd or no parity => Add configurable register, add command signal
  • 41.
    Exemple of UARTon µc 7- or 8-bit data with odd, even, or non-parity Independent transmit/receive shift registers Separate transmit and receive buffer registers LSB-first or MSB-first data transmit and receive Receiver start-edge detection for auto-wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression Independent interrupt capability for receive and transmit * TI / MSP430
  • 42.
    FPGA over-all Test When buttons is pushed , PC receive : [a]= 0x61 PC send data to FPGA : data are displayed on leds => Use HyperTerminal to send and receive data receiver transmitter start debounce data=[a]= 0x61 tx rx Data_ready data PC PC