VLSI testing and analysis

VLSI Testing and Analysis
Prof.Surekha Bhagwan Puri
HSBPVT’s COE KASHTI

Why Model Faults
 I/O function tests inadequate for manufacturing
 (functionality versus component and interconnection testing)
 Real defects (often mechanical) too numerous and often not
analyzable
 A fault model identifies targets for testing
 A fault model makes analysis possible
 Effectiveness measurable by experiments

 Defect, Fault, and Error
Defect: A defect is the unintended difference between the implemented hardware and its intended
design.
Defects occur either during manufacture or during the use of devices.
Fault: A representation of a defect at the abstracted function level.
Error: A wrong output signal produced by a defective system. An error is caused by a Fault or a
design error.
 Typical Types of Defects
 Extra and missing material
 Primarily caused by dust particles on the mask or
 wafer surface, or in the processing chemicals Oxide breakdown
 Primarily caused by insufficient oxygen at the interface of
 silicon (Si) and silicon dioxide (SiO2), chemical contamination,and crystal defects
Electromigration
 Primarily caused by the transport of metal atoms when a current flows through the wire

Logical Fault Models
 Systematic defects might be caused by process variations, signal integrity, and
design integrity issues.
 It is possible both random and systematic defects could happen on a single die
Logical faults
 Logical faults represent the physical defects on the
 behaviors of the systems

Role of Testing
 If you design a product, fabricate, and test it, and it fails the test,
 then there must because for the failure. Test was wrong
 The fabrication process was faulty
 The design was incorrect
 The specification problem
 The role of testing is to detect whether something went wrong and the role of
diagnosis is to determine exactly what went wrong.
 Correctness and effectiveness of testing is most important for
 quality products.

Verification & Test
 Verifies correctness of design
 Performed by simulation, hardware emulation, or formal methods
 Perform once before manufacturing
 Responsible for quality of design
Test
 Verifies correctness of manufactured hardware
 Two-part process
 Test generation: software process executed once during design
 Test application: electrical tests applied to hardware
 Test application performed on every manufactured device
 Responsible for quality of device

Types of Test
Production testing
Every fabricated chip is subjected to production tests
 The test patterns may not cover all possible functions and data patterns but must
have a high fault coverage of modeled faults
The main driver is cost, since every device must be tested.
 Test time must be absolutely minimized Only a go/no-go decision is made
 Test whether some device-under-test parameters are met to the device
specifications under normal operating conditions
 Burn-In testing
 Ensure reliability of tested devices by testing
 Detect the devices with potential failures

Test Process
The testing problem
Given a set of faults in the circuit under test (or device under test), how do we obtain a certain (small) number of
test patterns which guarantees a certain (high) fault coverage?
1. Test process
2. What faults to test? (fault modeling)
3. How are test pattern obtained? (test pattern generation)
How is test quality (fault coverage) measured?
(fault simulation)?
How are test vectors applied and results evaluated?

Testing & Diagnosis
Testing is a process which includes test
1. pattern generation, test pattern application, and output evaluation.
2. Fault detection tells whether a circuit is fault-free or not
3. Fault location provides the location of the detected fault
4. Fault diagnosis provides the location and the type of the detected fault

Fault Simulation
 Fault simulation
In general, simulating a circuit in the presence of faults is known as fault simulation
The main goals of fault simulation
1. Measuring the effectiveness of the test patterns
2. Guiding the test pattern generator program
3. Generating fault dictionaries
4. Outputs of fault simulation
5. Fault coverage - fraction (or percentage) of modeled faults
6. detected by test vectors
7. Set of undetected faults

Design for Testability
A fault is testable if there exists a well-specified procedure to expose it, which is implementable with a
reasonable cost using current technologies. A circuit is testable with respect to a fault set when each and every
fault in this set is testable
Definition
 Design for testability (DFT) refers to those design techniques that make test generation and test application
cost-effective
 Electronic systems contain three types of components:
(a) digital logic,
(b) memory blocks, and
(c) analog or mixed-signal circuits

WHAT IS DFT?
 Design for testability (DFT) refers to those design techniques that make test generation and
test application cost-effective.
 DFT consists of IC design techniques that add testability features to a hardware product
design.
 The purpose of manufacturing tests is to
 validate that the product hardware contains no
 manufacturing defects that could adversely

WHY DESIGN FOR TESTABILITY?
 Testability is a design characteristic that influences various costs associated with testing.It allows for:
 Device status to be determined
 Isolation of faults
 Reduce test time and cost
CONTROLLABILITY
 Ability to establish a specific signal value at each node by setting circuit’s inputs
 Circuits typically difficult to control: decoders,circuits with feedback, oscillators, clockgenerators …

OBSERVABILITY
 Ability to determine the signal value at any
 node in a circuit by controlling the circuit’s
 inputs and observing its output
 GOAL OF DESIGN FOR TESTABILITY(DFT)Improve
1. Controllability
2. Observability
3. Predictability

DFT METHODS
 DFT methods for digital circuits:
Ad-hoc methods
 Structured methods:
 Scan
 Partial Scan
 Built-in self-test (BIST)
 Boundary scan

AD-HOC DFT METHODS
 Good design practices learnt through experience are used as guidelines:
 Avoid asynchronous (un clocked) feedback
 Make flip-flops initializable
 Avoid redundant gates
 Avoid large fan-in gates
 Provide test control for difficult-to-control signals
 Avoid gated clocks
 Design reviews conducted by experts or design auditing tools
 Disadvantages of ad-hoc DFT methods:
 Experts and tools not always available
 Test generation is often manual with no guarantee of high fault coverage

SCAN DESIGN
 Circuit is designed using pre-specified design rules.
 Test structure (hardware) is added to the verified design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode.
 Make input/output of each scan shift register controllable/observable from PI/PO.
 Use only clocked D-type of flip-flops for all state variables
 At least one PI pin must be available for test; more pins, if available, can be used

BUILT-IN SELF-TEST
 Advances in microelectronics technology have
introduced a new paradigm in IC design: System-on- Chip (SoC)
 Many systems are nowadays designed by embedding
 predesigned and pre verified complex functional blocks
 (cores) into one single die
 Such a design style allows designers to reuse previous designs and will lead to shorter time-to-market and
reduced cost System-on-Chip
 Embedded DRAM Interface Control Copmplex core UDL Legacy core DSP core Self-test control
1149.1 UDL
 SoC structure breakdown:
 10% UDL
 75% memory
 50% in-house cores

BIST TECHNIQUES
 BIST techniques are classified:
 on-line BIST - includes concurrent and non-concurrent techniques
 off-line BIST - includes functional and structural approaches
 On-line BIST - testing occurs during normal functional operation
 Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques
or duplication and comparison are used
 Non-concurrent on-line BIST - testing is carried out while a system is in an idle state, often by
 executing diagnostic software or firmware routines
 Off-line BIST - system is not in its normal working mode, Usually
 on-chip test generators and output response analysers or micro diagnostic routines
 Functional off-line BIST is based on a functional description of the Component Under Test
 (CUT) and uses functional high-level fault models
 Structural off-line BIST is based on the structure of the CUT and uses structural fault models
 (e.g. SAF)

GENERAL ARCHITECTURE OF BIST
BIST components:
Test pattern generator (TPG)
Test response analyzer (TRA)
TPG & TRA are usually
implemented as linear feedback
shift registers (LFSR)
Two widespread schemes:
test-per-scan
test-per-clock

BIST BENEFITS
 Reduced testing and maintenance cost
 Lower test generation cost
 Reduced storage / maintenance of test patterns
 Simpler and less expensive ATE
 Can test many units in parallel
 Shorter test application times
 Can test at functional system speed

Introduction to Built-In Self-Test
Built-in self-test (BIST)
 The capability of a circuit (chip/board/system) to test itself
Advantages of BIST
 Test patterns generated on-chip -controllability Increased
 Test can be on-line (concurrent) or off-line
 Test can run at circuit speed, more realistic; shorter test time; easier delay testing
 External test equipment greatly simplified, or even totally eliminated
 Easily adopting to engineering changes

Benefits of Testing
 Quality and economy are two major benefits of testing
 The two attributes are greatly dependent and can not be defined without the other
 Quality means satisfying the user’s needs at a minimum cost
 The purpose of testing is to weed out all bad products before they reach the user
 The number of bad products heavily affect the price of good products
 A profound understanding of the principles of manufacturing and test is essential
for an engineer to design a quality product

DRAWBACKS OF BIST
 Additional pins and silicon area needed
 Decreased reliability due to increased silicon area
 Performance impact due to additional circuitry
 Additional design time and cost

JTAG and BOUNDARY SCAN
An outline of a typical test procedure using a
boundary scan is
as follows:
– A boundary-scan test instruction is shifted into the
IR
through the TDI.
– The instruction is decoded by the decoder
associated with the IR to generate the required
control signals so as to properly configure the test
logic.
– A test pattern is shifted into the selected data
register
through the TDI and then applied to the logic to be
tested.
– The test response is captured into some data
register.
– The captured response is shifted out through the
TDO
for observation and, at the same time, a new test
pattern can be scanned in through the TDI.

 How does it work?
The top level schematic of the test logic defined by IEEE Std 1149.1 includes three key blocks:
 The TAP Controller
This responds to the control sequences supplied through the test access port (TAP) and generates the
clock and control signals required for correct operation of the other circuit blocks.
 The Instruction Register
This shift register-based circuit is serially loaded with the instruction that selects an operation to be
performed.
 The Data Registers
These are a bank of shift register based circuits. The stimuli required by an operation are serially
loaded into the data registers selected by the current instruction. Following execution of the
operation, results can be shifted out for examination.

 The function of each TAP pin is as follows:
 n TCK - this pin is the JTAG test clock. It sequences the TAP controller as well as
all of the JTAG registers
 n TMS - this pin is the mode input signal to the TAP Controller. The state of TMS
at the rising edge of TCK determines the sequence of states for the TAP
controller.
 TDI - this pin is the serial data input to all JTAG instruction and data registers.
TDI is sampled into the JTAG registers on the rising edge of TCK.
 TDO - this pin is the serial data output for all JTAG instruction and data
registers.. TDO changes state on the falling edge of TCK and is only active
during the shifting of data through the device. This pin is three-stated at all other
times

Test Access Port Controller
 n The JTAG Test Access Port (TAP) contains four pins that drive the
circuit blocks and control the operations specified.
 The TAP facilitates the serial loading and unloading of
 instructions and data.
 The four pins of the TAP are:
 n TMS – Test Mode Select
 n TCK – Test Clock
 n TDI - Test Data Input
 n TDO – Test Data Output

 The JTAG TAP Controller is a
1. 16-state finite state machine, that controls the scanning of data into the various
registers of the JTAG architecture.
2. The state of the TMS pin at the rising edge of TCK is responsible for determining
the sequence of state transitions.
3. There are two state transition paths for scanning the signal at
TDI in to the device,
one for shifting in an instruction to the instruction register ,and , one for shifting
data into the active data register as determined by the current instruction.

Data Registers
The Device ID register (IDR) reads-out an identification
number which is hardwired into the chip.
The Bypass register (BR) is a 1-cell pass-through register
which connects the TDI to the TDO with a1-clock delay to
give test equipment easy access to another device in the test
chain on the same board.
The Boundary Scan register (BSR), intercepts all the signals
between the core-logic and the pins.

TEST PROCESS
 The standard test process for verifying a device or circuit board using boundary-
scan technology is as follows:
 The tester applies test or diagnostic data on the input pins of the device.
 The boundary-scan cells capture the data in the boundary scan registers
monitoring the input pins.
 Data is scanned out of the device via the TDO pin,for verification.
 Data can then be scanned into the device via theTDI pin.
 The tester can then verify data on the output pins of the device.

AUTOMATIC TEST PATTERN
GENERATION
 Automatic test equipment (ATE) is computer-controlled equipment used in
 the production testing of ICs (both at the wafer level and in packaged devices)
and PCBs.
 Test patterns are applied to the CUT and the output responses are compared to
stored responses for the fault free circuit.
 Generating effective test patterns efficiently for a digital circuit is thus the goal of
any Automatic-Test-Pattern- Generation (ATPG) system.
 The effectiveness of ATPG is measured by the number of modeled defects, or
fault models, detectable and by the number of generated patterns

Sequential ATPG
 Sequential-circuit ATPG searches for a sequence of test vectors to
detect a particular fault through the space of all possible test vector
sequences.
 Even a simple stuck-at fault requires a sequence of vectors for
detection in a sequential circuit.
 Due to the presence of memory elements, the controllability and
observability of the internal signals in a sequential circuit are in
general much more difficult than those in a combinational logic
circuit.

PATH SENSITIZATION
 Fault Sensitization
 Fault Propagation
 Line Justification

 Try path f – h – k – L. This path is
 blocked at j, since there is no way to
 justify the 1 on i

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