[TRTLLM-5966][feat] Helix: add custom position ids to MLA kernels #6904
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📝 WalkthroughWalkthroughAdds optional helix_position_offsets support across CUDA kernel, C++ attention op, nanobind/pybind bindings, and Python TRT-LLM attention. Consolidates MLA-related inputs into an Changes
Sequence Diagram(s)sequenceDiagram
participant Py as TrtllmAttention.forward
participant Wr as TrtllmAttentionWrapper
participant Op as attention (C++)
participant Run as Runner::run
participant K as applyMLARopeAndAssignQKVKernelGeneration
Py->>Wr: plan(..., helix_position_offsets)
Wr->>Wr: store helix_position_offsets
Py->>Wr: run(...)
Wr->>Op: attention(..., mla_tensor_params=[ctx_paged_kv, kv_block_offsets, helix_pos_offsets], ...)
Op->>Run: Runner::run(..., mla_tensor_params, ...)
Run->>K: launch(..., helix_position_offsets)
K->>K: position_id = helix_pos_offsets ? override : default
Estimated code review effort🎯 4 (Complex) | ⏱️ ~35 minutes Possibly related PRs
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Actionable comments posted: 7
🔭 Outside diff range comments (1)
cpp/tensorrt_llm/thop/attentionOp.cpp (1)
167-175: Bounds-check mla_tensor_params before indexing [0] and [1] to prevent OOBAccessing mla_tensor_params[0] and [1] without checking size risks out-of-bounds access if the caller provides fewer entries. Also make refs const to reflect read-only usage.
Apply this diff:
- auto& mla_context_paged_kv = mla_tensor_params[0]; - auto& mla_context_kv_cache_block_offsets = mla_tensor_params[1]; + TORCH_CHECK( + mla_tensor_params.size() > 1, + "mla_tensor_params must contain at least 2 tensors: [0]=context_paged_kv, [1]=context_kv_cache_block_offsets"); + auto const& mla_context_paged_kv = mla_tensor_params[0]; + auto const& mla_context_kv_cache_block_offsets = mla_tensor_params[1]; TORCH_CHECK(mla_context_paged_kv.has_value()); TORCH_CHECK(mla_context_kv_cache_block_offsets.has_value()); mla_params.context_paged_kv_ptr = mla_context_paged_kv->data_ptr(); mla_params.context_kv_cache_block_offsets_ptr = mla_context_kv_cache_block_offsets->data_ptr(); mla_params.context_paged_kv_max_blocks_per_seq = mla_context_kv_cache_block_offsets->size(-1);Optional (readability): document the expected layout locally.
// mla_tensor_params layout: [0]=context_paged_kv, [1]=context_kv_cache_block_offsets, [2]=helix_position_offsets (optional)
🧹 Nitpick comments (5)
cpp/tensorrt_llm/kernels/mlaKernels.h (1)
93-94: Helix offsets plumbed into MlaParams — looks good; clarify contract (shape/index space).The addition is correct and non-intrusive. Please clarify the expected index space and shape in the comment to avoid confusion at call sites (global token index across the entire batch, device pointer). This helps prevent subtle misuse.
Apply this diff to enrich the comment:
- // for Helix parallelism: the rotary position offsets [b] - int32_t const* helix_position_offsets{nullptr}; + // For Helix parallelism: rotary position offsets in global-token index space. + // Shape: [total_s_len] (sum of per-seq lengths), device pointer on CUDA. + // When nullptr, the default positional indexing is used by the kernels. + int32_t const* helix_position_offsets{nullptr};tensorrt_llm/_torch/attention_backend/trtllm.py (2)
223-223: Fix line too long (Ruff E501) in docstring.Split the helix_position_offsets docstring line to stay within the 120-char limit.
- helix_position_offsets (torch.Tensor): The tensor to store the helix position offsets, with shape (num_tokens) on GPU. + helix_position_offsets (torch.Tensor): The tensor to store the helix position offsets, + with shape (num_tokens) on GPU.
1113-1114: Forward API: helix_position_offsets threading is OK; add a short docstring note.The param is optional and does not change default behavior. Consider documenting its expected shape/dtype to guide users.
cpp/tensorrt_llm/thop/attentionOp.cpp (2)
80-83: Avoid copying MLA tensor params; pass by ArrayRef like spec-decoding tensorsPass mla_tensor_params as c10::ArrayRef to avoid an extra vector copy and to align with the spec_decoding_tensor_params pattern.
Apply this diff to the RunnerBase::run signature:
- std::vector<std::optional<torch::Tensor>> mla_tensor_params, + c10::ArrayRef<std::optional<torch::Tensor>> mla_tensor_params,
134-137: Mirror ArrayRef change in Runner::run overrideKeep the override consistent with the base class, and avoid copies here as well.
Apply this diff to the Runner::run signature:
- std::vector<std::optional<torch::Tensor>> mla_tensor_params, + c10::ArrayRef<std::optional<torch::Tensor>> mla_tensor_params,
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📒 Files selected for processing (6)
cpp/tensorrt_llm/kernels/mlaKernels.cu(3 hunks)cpp/tensorrt_llm/kernels/mlaKernels.h(1 hunks)cpp/tensorrt_llm/nanobind/thop/bindings.cpp(1 hunks)cpp/tensorrt_llm/pybind/thop/bindings.cpp(1 hunks)cpp/tensorrt_llm/thop/attentionOp.cpp(7 hunks)tensorrt_llm/_torch/attention_backend/trtllm.py(7 hunks)
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cpp/tensorrt_llm/kernels/mlaKernels.hcpp/tensorrt_llm/pybind/thop/bindings.cppcpp/tensorrt_llm/nanobind/thop/bindings.cppcpp/tensorrt_llm/thop/attentionOp.cppcpp/tensorrt_llm/kernels/mlaKernels.cu
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223-223: Line too long (130 > 120)
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🔇 Additional comments (6)
cpp/tensorrt_llm/kernels/mlaKernels.cu (2)
362-363: Kernel signature extension is consistent and preserves ordering.The extra parameter is appended at the end, keeping ABI alignment with the launch site. No concerns.
999-999: Host-side wiring passes helix offsets correctly.The added argument is forwarded in the proper position to match the kernel signature.
tensorrt_llm/_torch/attention_backend/trtllm.py (2)
180-181: Plan API: helix_position_offsets exposure is fine.The new parameter is threaded cleanly through plan() and forward(). Ensure downstream validation to avoid dtype/device mismatches.
489-489: Wrapper forwards mla_tensor_params correctly.The binding call site matches the updated pybind/nanobind signatures.
cpp/tensorrt_llm/thop/attentionOp.cpp (2)
683-685: LGTM: correctly forwards MLA params for context stageThe added mla_tensor_params and softmax_stats_tensor/spec params are forwarded in the right order to Runner::run.
699-701: LGTM: correctly forwards MLA params for generation stageThe generation call mirrors the context call and keeps the same parameter ordering.
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Actionable comments posted: 2
🧹 Nitpick comments (2)
cpp/tensorrt_llm/thop/attentionOp.cpp (2)
80-80: Avoid copies: accept mla_tensor_params as ArrayRef in Runner interfacesThe vector is passed by value into RunnerBase::run and Runner::run, causing unnecessary copies. Use c10::ArrayRef (consistent with spec_decoding_tensor_params) to avoid allocations and copying.
Apply these diffs:
- std::vector<std::optional<torch::Tensor>> mla_tensor_params, + c10::ArrayRef<std::optional<torch::Tensor>> mla_tensor_params,- std::vector<std::optional<torch::Tensor>> mla_tensor_params, + c10::ArrayRef<std::optional<torch::Tensor>> mla_tensor_params,Also applies to: 134-134
165-172: Replace magic indices (0/1/2) with named constexpr constantsPer guidelines (avoid magic numbers), introduce named indices to improve readability and reduce error-proneness.
Apply this diff:
- TORCH_CHECK(mla_tensor_params.size() == 3, + TORCH_CHECK(mla_tensor_params.size() == 3, "Expecting 3 tensors for custom MLA tensor params: context_paged_kv, " "context_kv_cache_block_offsets, helix_position_offsets."); + constexpr size_t kMlaContextPagedKvIdx = 0; + constexpr size_t kMlaContextKvCacheBlockOffsetsIdx = 1; + constexpr size_t kMlaHelixPositionOffsetsIdx = 2; if (is_context && op.mPagedContextFMHA && op.mPagedKVCache) { - auto& mla_context_paged_kv = mla_tensor_params[0]; - auto& mla_context_kv_cache_block_offsets = mla_tensor_params[1]; + auto const& mla_context_paged_kv = mla_tensor_params[kMlaContextPagedKvIdx]; + auto const& mla_context_kv_cache_block_offsets = mla_tensor_params[kMlaContextKvCacheBlockOffsetsIdx]; TORCH_CHECK(mla_context_paged_kv.has_value()); TORCH_CHECK(mla_context_kv_cache_block_offsets.has_value()); @@ - auto& mla_helix_position_offsets = mla_tensor_params[2]; - if (mla_helix_position_offsets.has_value()) + auto const& mla_helix_position_offsets = mla_tensor_params[kMlaHelixPositionOffsetsIdx]; + if (mla_helix_position_offsets.has_value()) { mla_params.helix_position_offsets = mla_helix_position_offsets->data_ptr<int32_t>(); }Also applies to: 205-209
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Use Allman brace style in C++
C++ filenames use lowerCamelCase and must be case-insensitively unique within a build target
C++ type names use UpperCamelCase
Local variables, methods, and namespaces use lowerCamelCase
Global non-static variables not in anonymous namespace use gPrefix lowerCamelCase (e.g., gExample)
Static globals or globals in anonymous namespaces use sPrefix lowerCamelCase
Locally visible static variables start with 's' (e.g., static std::once_flag sFlag;)
Member variables use mPrefix lowerCamelCase; public members may omit but are encouraged to use 'm'
Constants (enums, global/static/function-scope magic numbers) use kPREFIXED_UPPER_SNAKE (e.g., kDIGIT_NUM)
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Capitalize and punctuate full-sentence comments
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🧠 Learnings (3)
📚 Learning: 2025-08-14T15:41:16.775Z
Learnt from: MatthiasKohl
PR: NVIDIA/TensorRT-LLM#6904
File: cpp/tensorrt_llm/thop/attentionOp.cpp:202-206
Timestamp: 2025-08-14T15:41:16.775Z
Learning: The PyTorch tensor's templated data_ptr<T>() method automatically validates that the tensor's dtype matches the requested type T and will throw a runtime error if there's a mismatch, making explicit dtype checks redundant before calling data_ptr<T>().
Applied to files:
cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-08-14T15:38:01.730Z
Learnt from: MatthiasKohl
PR: NVIDIA/TensorRT-LLM#6904
File: cpp/tensorrt_llm/pybind/thop/bindings.cpp:55-57
Timestamp: 2025-08-14T15:38:01.730Z
Learning: In TensorRT-LLM Python bindings, tensor parameter collections like mla_tensor_params and spec_decoding_tensor_params are kept as required parameters without defaults to maintain API consistency, even when it might affect backward compatibility.
Applied to files:
cpp/tensorrt_llm/thop/attentionOp.cpp
📚 Learning: 2025-08-14T15:43:23.067Z
Learnt from: MatthiasKohl
PR: NVIDIA/TensorRT-LLM#6904
File: tensorrt_llm/_torch/attention_backend/trtllm.py:259-262
Timestamp: 2025-08-14T15:43:23.067Z
Learning: In TensorRT-LLM's attention backend, tensor parameters in the plan() method are assigned directly without validation (dtype, device, contiguity checks). This maintains consistency across all tensor inputs and follows the pattern of trusting callers to provide correctly formatted tensors.
Applied to files:
cpp/tensorrt_llm/thop/attentionOp.cpp
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🔇 Additional comments (2)
cpp/tensorrt_llm/thop/attentionOp.cpp (2)
686-687: LGTM: Correctly forwards new mla_tensor_params to RunnerThe updated call sites forward mla_tensor_params and keep spec_decoding_tensor_params ordering consistent with the Runner signature.
Also applies to: 702-703
165-168: Verified — no change required: all call sites pass 3 MLA tensorsShort summary: I searched the repo and confirmed the MLA tensor list is constructed with exactly three entries in the Python backend and is forwarded through the bindings; the C++ check (size()==3) matches the call sites. The helix_position_offsets entry is allowed to be None and is handled in the C++ code.
Files of interest:
- cpp/tensorrt_llm/thop/attentionOp.cpp:165-172 (TORCH_CHECK(mla_tensor_params.size() == 3) and indexing [0],[1]) and 205-207 (uses mla_tensor_params[2] with has_value() check).
- tensorrt_llm/_torch/attention_backend/trtllm.py:425-427 — mla_tensor_params = [self.mla_context_paged_kv, self.mla_context_kv_cache_block_offsets, self.helix_position_offsets]
- cpp/tensorrt_llm/pybind/thop/bindings.cpp and cpp/tensorrt_llm/nanobind/thop/bindings.cpp — mla_tensor_params exposed as a function argument.
Result: no further action required here; the strict size()==3 check is consistent with current call sites.
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Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com>
Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com>
Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com>
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…IDIA#6904) Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com> Co-authored-by: brb-nv <169953907+brb-nv@users.noreply.github.com>
…IDIA#6904) Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com> Co-authored-by: brb-nv <169953907+brb-nv@users.noreply.github.com>
…IDIA#6904) Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com> Co-authored-by: brb-nv <169953907+brb-nv@users.noreply.github.com>
…IDIA#6904) Signed-off-by: Matthias Jouanneaux <mjoux@nvidia.com> Co-authored-by: brb-nv <169953907+brb-nv@users.noreply.github.com>
3 participants
Summary by CodeRabbit
New Features
Refactor
Description
This PR adds the possibility of using custom position IDs for MLA generation, in the MLA kernels. This is useful for Helix to allow the different GPUs to obtain the right RoPE parameters for the output token even if it is at a much later position in the full sequence (compared to the local sequence of the GPU).
Test Coverage
No tests are needed as this PR only makes the feature available and does not actually call it anywhere.
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