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[TRTLLM-6286] [perf] Add NoSmem epilogue schedule and dynamic cluster shape for sm10x group gemm by VALLIS-NERIA · Pull Request #7757 · NVIDIA/TensorRT-LLM · GitHub
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@VALLIS-NERIA VALLIS-NERIA commented Sep 16, 2025

Summary by CodeRabbit

  • Refactor
    • Gated Blackwell (SM103) execution path behind a compile-time option and improved the runtime message to clearly instruct rebuilding with Blackwell support for optimal performance.
  • Chores
    • Updated a third-party dependency to a newer revision.
    • Simplified kernel generation by removing a runtime file-patching step, improving build robustness and maintainability.

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Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
@VALLIS-NERIA VALLIS-NERIA requested a review from djns99 September 16, 2025 07:58
@VALLIS-NERIA VALLIS-NERIA self-assigned this Sep 16, 2025
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@djns99 I'm not quite sure how the gtests are compiled. Can you give some hints about covering both sm100f and sm103 kernels?

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📝 Walkthrough

Walkthrough

Updated CUTLASS submodule to a newer commit. Added a compile-time guard and revised logging for the Arch==103 MoE GEMM path. Removed runtime file-patching logic from the kernel generation Python script.

Changes

Cohort / File(s) Summary
CUTLASS submodule update
3rdparty/cutlass
Advanced submodule pointer from a49a78f... to 57e3cfb...; no project code changes.
MoE GEMM Blackwell arch guard & log
cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h
Activated preprocessor guard to gate Arch==103 path behind COMPILE_BLACKWELL_SM103_TMA_GROUPED_GEMMS; updated warning message formatting/content; minor formatting tweaks.
Kernel generation script cleanup
cpp/tensorrt_llm/kernels/cutlass_kernels/python/generate_kernels.py
Removed runtime patching of heuristics_provider.py; retains direct cutlass_library.* imports; no other functional edits.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  actor Dev as Developer/Build
  participant CPP as MoE GEMM (C++)
  participant Macro as Compile-time Macro
  participant Log as Logger

  Dev->>CPP: Build with/without Blackwell macro
  Note over Macro,CPP: Guard Arch==103 path behind<br/>COMPILE_BLACKWELL_SM103_TMA_GROUPED_GEMMS
  alt Macro enabled (Blackwell support compiled)
    CPP->>CPP: Enable Arch==103 code path
  else Macro not enabled
    CPP->>Log: Emit instruction to compile with 103-real
  end
Loading
sequenceDiagram
  autonumber
  actor User as Dev/CI
  participant Py as generate_kernels.py
  participant Lib as cutlass_library
  User->>Py: Run kernel generation
  Py->>Lib: Import cutlass_library (no runtime patching)
  Py->>User: Generate kernels as configured
  Note over Py: Removed file editing of heuristics_provider.py
Loading

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~10 minutes

Pre-merge checks and finishing touches

❌ Failed checks (2 warnings)
Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%. You can run @coderabbitai generate docstrings to improve docstring coverage.
Description Check ⚠️ Warning The submitted PR description contains only the repository PR template text and is not filled out with author-provided details; it therefore lacks the required title line in the "[TICKET][type] Summary" format, a populated "Description" explaining what and why, an explicit "Test Coverage" section, and a completed PR Checklist. Because these required sections are empty or left as template placeholders, reviewers cannot assess the scope, rationale, tests performed, or any compatibility/build notes for the change. This makes the PR description largely incomplete and insufficient for review. Please update the PR description to include a proper title following the template (for example "[TRTLLM-6286][feat] Update CUTLASS to 4.2 and enable SM103 group GEMM"), a concise "Description" that explains the code changes and rationale, a "Test Coverage" section listing the exact tests/CI stages run and their results, and a completed PR Checklist. Also add any relevant build/compatibility notes (required compile flags, supported GPUs), reproduction steps for new paths, and links to CI/pipeline runs or performance/regression results so reviewers can validate the change.
✅ Passed checks (1 passed)
Check name Status Explanation
Title Check ✅ Passed The title "[TRTLLM-6286] [perf] Add NoSmem epilogue schedule and dynamic cluster shape for sm10x group gemm" is concise, includes a ticket and type tag, and describes a concrete improvement to sm10x grouped GEMM performance. However, the PR summaries and objectives primarily show a CUTLASS submodule update and gating/enabling of SM103 group GEMM with small header and script edits, and they do not describe an explicit NoSmem epilogue or dynamic-cluster-shape implementation, so the title only partially reflects the actual changeset. Because it references a real aspect (group GEMM) but omits the principal CUTLASS update, the title is acceptable but should be aligned to the main change for clarity.
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Actionable comments posted: 1

🧹 Nitpick comments (3)
3rdparty/cutlass (2)

1-1: Prefer tracking a release tag (or document the exact CUTLASS version).

For reproducibility, consider referencing a tagged release (or add a note in RELEASE_NOTES/DEPS.md mapping this SHA → “CUTLASS 4.2”).


1-1: Compliance and toolchain checklist for SM103.

  • Update third_party notices/SBOM if required by policy.
  • Ensure CI uses a CUDA toolkit/NVCC that supports sm_103 and that build flags include 103-real where needed.
  • Add/keep a focused perf/regression test that exercises SM103 grouped GEMM.
cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h (1)

156-156: Optional: annotate #endif with macro name

Add the macro name to ease scanning large guard stacks.

-#endif
+#endif // !COMPILE_BLACKWELL_SM103_TMA_GROUPED_GEMMS
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Reviewing files that changed from the base of the PR and between b278d06 and 61973a9.

📒 Files selected for processing (3)
  • 3rdparty/cutlass (1 hunks)
  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h (1 hunks)
  • cpp/tensorrt_llm/kernels/cutlass_kernels/python/generate_kernels.py (0 hunks)
💤 Files with no reviewable changes (1)
  • cpp/tensorrt_llm/kernels/cutlass_kernels/python/generate_kernels.py
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🧠 Learnings (3)
📓 Common learnings
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#7104
File: cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/epilogue/fusion/sm90_visitor_scatter.hpp:399-417
Timestamp: 2025-08-21T21:48:35.135Z
Learning: CUTLASS extensions in TensorRT-LLM (located under cpp/tensorrt_llm/cutlass_extensions/) are designed to integrate with and extend functionality in the external CUTLASS repository. When analyzing these extensions, their consumers and functionality wiring may exist in the CUTLASS codebase rather than within TensorRT-LLM itself.
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h
📚 Learning: 2025-08-21T02:39:12.009Z
Learnt from: djns99
PR: NVIDIA/TensorRT-LLM#7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1475-1480
Timestamp: 2025-08-21T02:39:12.009Z
Learning: The min latency mode functionality in TensorRT-LLM MOE kernels (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu) is deprecated and no longer being maintained/updated, as confirmed by djns99. Bug reports and optimization suggestions for the computeStridesTmaWarpSpecializedLowLatencyKernel and related min latency code paths should be deprioritized.

Applied to files:

  • cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h
🧬 Code graph analysis (1)
cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h (2)
cpp/tensorrt_llm/cutlass_extensions/include/cutlass_extensions/gemm_configs.h (12)
  • if (308-311)
  • if (312-315)
  • if (316-319)
  • if (320-323)
  • if (324-327)
  • if (328-331)
  • if (332-335)
  • if (336-339)
  • if (340-343)
  • if (488-495)
  • if (496-499)
  • ClusterShape (267-430)
cpp/include/tensorrt_llm/kernels/archCondition.h (1)
  • arch (72-111)
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🔇 Additional comments (2)
3rdparty/cutlass (1)

1-1: CUTLASS submodule bump — LGTM; verify SHA -> tag and SM103 end-to-end

  • Local git describe returned 61973a9 and submodule status shows -57e3cfb...; no annotated tag present locally. Verify with:
    git -C 3rdparty/cutlass fetch --tags && git -C 3rdparty/cutlass describe --tags --contains 61973a9 || git -C 3rdparty/cutlass tag --contains 61973a9
    Confirm it maps to CUTLASS v4.2 (or move the submodule to the annotated tag).

  • SM103 wiring present but needs build verification:

    • CMake adds COMPILE_BLACKWELL_SM103_TMA_GROUPED_GEMMS (cpp/tensorrt_llm/kernels/cutlass_kernels/CMakeLists.txt:95).
    • Code falls back and instructs recompilation with "103-real" (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h:150 and cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/launchers/moe_gemm_tma_ws_launcher.inl:145).
    • Generator imports cutlass_library (cpp/tensorrt_llm/kernels/cutlass_kernels/python/generate_kernels.py:6) — no runtime patching.
      Confirm build_wheel.py accepts/maps "103-real" into the CMAKE arch list (check build_wheel.py or run: rg -n "103-real|CMAKE_CUDA_ARCHITECTURES" -S) so grouped SM103 GEMMs are produced and compiled end-to-end.
cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_template_dispatch_tma_ws.h (1)

149-151: Warning text change LGTM

Message clearly communicates SM103 best‑performance guidance and is single-shot via call_once. No action needed.

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djns99 commented Sep 18, 2025

@djns99 I'm not quite sure how the gtests are compiled. Can you give some hints about covering both sm100f and sm103 kernels?

Running the tests on SM103 should be sufficient with these changes. The new logic in the selectTacticsForArch() ensures we run tests for both pathways

Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
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@VALLIS-NERIA VALLIS-NERIA changed the title [TRTLLM-6286] [feat] Update CUTLASS to 4.2 and enable SM103 group gemm [TRTLLM-6286] [perf] Add NoSmem epilogue schedule and dynamic cluster shape for sm10x group gemm Sep 18, 2025
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djns99 and others added 4 commits September 18, 2025 15:07
Signed-off-by: Daniel Stokes <dastokes@nvidia.com>

Various updates and tweaks

Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>

Rebase fixes

Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>

Fix rebase issues

Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>

Fix incorrect compilation of SM80 kernels

Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>

Correctly test SM103 and SM100 test configs on GB300

Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>
Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
@VALLIS-NERIA VALLIS-NERIA force-pushed the user/xiweny/cutlas-update branch from d05cef1 to c1926da Compare September 18, 2025 10:30
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VALLIS-NERIA and others added 2 commits September 19, 2025 10:21
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@VALLIS-NERIA VALLIS-NERIA enabled auto-merge (squash) September 19, 2025 05:03
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PR_Github #19277 [ run ] triggered by Bot

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PR_Github #19277 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #14479 completed with status: 'FAILURE'

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PR_Github #19345 [ run ] triggered by Bot

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PR_Github #19370 [ run ] triggered by Bot

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PR_Github #19370 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #14548 completed with status: 'SUCCESS'

@VALLIS-NERIA VALLIS-NERIA merged commit 822cb01 into NVIDIA:main Sep 21, 2025
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@VALLIS-NERIA VALLIS-NERIA deleted the user/xiweny/cutlas-update branch September 21, 2025 03:39
MrGeva pushed a commit to nv-auto-deploy/TensorRT-LLM that referenced this pull request Sep 21, 2025
… shape for sm10x group gemm (NVIDIA#7757)

Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
nv-lschneider pushed a commit to nv-lschneider/TensorRT-LLM that referenced this pull request Sep 22, 2025
… shape for sm10x group gemm (NVIDIA#7757)

Signed-off-by: Xiwen Yu <13230610+VALLIS-NERIA@users.noreply.github.com>
Signed-off-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
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3 participants