-
Notifications
You must be signed in to change notification settings - Fork 938
Basic RISC-V support #644
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Basic RISC-V support #644
Conversation
|
Thanks, that sounds interesting. I'll take a look. How do you see the future maintenance of RISC-V port? Currently, I can't guarantee that ongoing development will keep the port functioning or even buildable. |
I can take a look at it every once in a while, or maybe someone from RISC-V community takes on that role too. I wonder if there is a way to integrate the support for these arches under heavy "It would probably build, it would probably work, but it is not tested well" caveat warnings. |
|
We could have a minimum of cross-compilation even if we don't run any tests. I'm happy to take a look at it in the future (working on Java on RISC-V now). |
|
Hi, Let me revive this please. Turns out that @zifeihan from my team has real-world working experience with the async-profiler tool. @zifeihan: Could you please post your extra changes needed for the latest codebase and the test results? |
|
@shipilev Hello aleksey, Following extra change is needed to make this buildable with latest async-profiler code: diff --git a/src/arch.h b/src/arch.h
index 46842fd..5f1c6df 100644
--- a/src/arch.h
+++ b/src/arch.h
@@ -128,6 +128,7 @@ const int BREAKPOINT_OFFSET = 0;
const int SYSCALL_SIZE = sizeof(instruction_t);
const int FRAME_PC_SLOT = 1; // return address is at -1 from FP
const int ADJUST_RET = 0; // No need for adjustments
+const int PROBE_SP_LIMIT = 0;
const int PLT_HEADER_SIZE = 24; // Best guess from examining readelf
const int PLT_ENTRY_SIZE = 24; // ...same...
const int PERF_REG_PC = 0; // PERF_REG_RISCV_PCCould you please add this into this PR? Thanks. And this is the detailed test output using latest async-profiler codebase on Linux-riscv64 platform: And I have also collected the sampling results for several test items from specjvm2008 and compared with results on linux-aarch64 platform. Sampling results look good. @apangin : Could you please take a look at these changes? Thanks |
Added! |
|
Hi and thank you for working on this. I have nothing against the content, however, the project does not accept external code contributions at this moment. This is temporary. I'll get back to you as soon as I resolve the blockers. I appreciate your patience. |
6a0e2ee to
1fc609c
Compare
|
Thank you for the contribution. I merged the PR with the minor follow-up fixes. |
|
Hi, it's great to see this merged. I also performed |
This PR adds the support for building and running on riscv64 platforms. I have built and tested it on HiFive Unmatched board running Ubuntu 22.04, and ran async-profiler with JMH -prof async and bleeding edge mainline JDK 20 build. The flamegraphs seem to make sense: it resolves C2 native code well, resolves compiled code well, etc.
I tested with
-Xint,-XX:TieredStopAtLevel=1(C1), default (C2).I still call this support "basic", because it is not tested beyound toy examples, and some features (like stub pops) are stubbed out.