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Modelsim Tutorial

This document provides instructions for using the ModelSim software to simulate VHDL code for digital circuits in an embedded systems lab. It includes a code of ethics for the lab, details downloading and installing ModelSim, steps for executing and simulating VHDL code using ModelSim, and an example of a 4-bit adder circuit coded in VHDL including both structural and behavioral implementations.

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Richard Becker
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62 views15 pages

Modelsim Tutorial

This document provides instructions for using the ModelSim software to simulate VHDL code for digital circuits in an embedded systems lab. It includes a code of ethics for the lab, details downloading and installing ModelSim, steps for executing and simulating VHDL code using ModelSim, and an example of a 4-bit adder circuit coded in VHDL including both structural and behavioral implementations.

Uploaded by

Richard Becker
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Advance Digital Design

Embedded Systems
Laboratory

EE 270
(Room#389)

CODE OF ETHICS
No eating or drinking is allowed inside lab
Switch off the lights and computers if not in
use
Use lab only for project and assignments

DO NOT USE THE COMPUTERS IN


LAST TWO ROWS

ModelSim
User-friendly software accepting VHDL and
Verilog.
Compatible with any Windows versions
Download free student version from the
below link:
http://www.mentor.com/company/higher_ed/m
odelsim-student-edition

Steps to download Modelsim:


Download .exe file for ModelSim and start
installing it
Fill up the license request form (mention
college address in this form)
License .dat file will be mailed on the email
address given in the form
Copy that file in ModelSims folder
Run a simple code to check if its working

Executing VHDL Code in ModelSIM


Open ModelSim and create new source file to
write the code(FILE tab from menubar)

Save the file with .vhdl extension or else it


will save it as text by default

Compile the code by selecting the file saved

Once compilation is finished(correct the errors if any


before simulating), simulate after selecting the file from
work folder.

To check waveforms, check ADD tab. Go for


To wave All items in design

Force the values of inputs by right clicking on


the input variable in the blue pane.

Now run and see the waveforms by trying


various input condition

If you want to see the schematic generated by your VHDL code


you can add the design to the Dataflow

Screen showing schematic diagram

Full Adder- Structural type Code


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c_in : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
c_out : out STD_LOGIC);
end adder_4bit;
architecture Behavioral of adder_4bit is
signal c: std_logic_vector (3 downto 0);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
begin
FA0: FULLADDER port map (a(0), b(0), c_in, sum(0), c(0));
FA1: FULLADDER port map (a(1), b(1), c(0), sum(1), c(1));
FA2: FULLADDER port map (a(2), b(2), c(1), sum(2), c(2));
FA3: FULLADDER port map (a(3), b(3), c(2), sum(3), c(3));
c_out <= c(3);
end Behavioral;

Continued(Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;

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