ROGRAM NO: 1

AIM: Write HDL code to realize all the logic gates

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity gates is
Port ( Ain : in std_logic; ---- First Input
Bin : in std_logic; ---- Second Input
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
end gates;
architecture Behavioral of gates is
begin
Op_not <= not Ain;
Op_or <= Ain or Bin;
Op_and <= Ain and Bin;
Op_nor <= Ain nor Bin;
Op_nand <= Ain nand Bin;
Op_xor <= Ain xor Bin;
Op_xnor <= Ain xnor Bin;
end Behavioral;
Verilog Program

module all_gates(Ain,Bin, Op_not, Op_or, Op_and, Op_nor, Op_nand, Op_xor, Op_xnor);

input Ain,Bin;

output Op_not, Op_or, Op_and, Op_nor, Op_nand, Op_xor, Op_xnor;

assing Op_not = ~Ain;

assing Op_or = Ain | Bin;

assing Op_and = Ain & Bin;

assing Op_nor = ~(Ain | Bin);

assing Op_nand = ~(Ain & Bin);

assing Op_xor = Ain ^ Bin;

assing Op_xnor = ~(Ain ^ Bin);

endmodule
PROGRAM NO: 2

AIM: Write HDL programme for the following combinational designs

a) 2 to 4 decoder in Dataflow modelling.

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity d2_4mx is
port ( a,b: in std_logic;
s0,s1 : in std_logic;
y0,y1,y2,y3 : out std_logic);
end d2_4mx;

architecture behave of d2_4mx is

begin
y0 <= (not a) and (not b) and (not s1) and (not s0);
y1 <= ( not a ) and b and ( not s1) and s0;
y2 <= a and ( not b ) and s1 and ( not s0 );
y3 <= a and b and s1 and s0;
end behave;

Verilog Program

module dec2_4(a,b,s0,s1,y0,y1,y2,y3);
input a,b,s0,s1;
output y0,y1,y2,y3;

assign y0 = (~a & ~b) & (~s1 & ~s0);

assign y1 = (~a & b) & (~s1 & s0);
assign y2 = (a & ~b) & (s1 & ~s0);
assign y3 = (a & b) & (s1 & s0);
endmodule
 b) Multiplexer, de-multiplexer, comparator

1) Multiplexer 8to1in dataflow modeling.

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity mux8_1 is
port (I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2: in std_logic;
y:out std_logic);
end mux8_1;

architecture Behavioral of mux8_1 is

begin
y <= (not s2 and not s1 and not s0 and I0 ) or
( not s2 and not s1 and s0 and I1 ) or
( not s2 and s1 and not s0 and I2 ) or
( not s2 and s1 and s0 and I3 ) or
( s2 and not s1 and not s0 and I4 ) or
( s2 and not s1 and s0 and I5 ) or
( s2 and s1 and not s0 and I6 ) or
( s2 and s1 and s0 and I7 );
end Behavioral;
2) Multiplexer 8to1behavioral modeling .
VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity eight_onemux is

port(a,b,c,d,e,f,g,h:in std_logic_vector(7 downto 0);

sel:in std_logic_vector(2 downto 0);

output:out std_logic_vector(7 downto 0));

end eight_onemux;

Architecture behave of eight_onemux is

begin

process(a,b,c,d,e,f,g,h,sel)

variable y:std_logic_vector(7 downto 0);

begin

if(sel="000") then

y:=a;

elsif

(sel="001") then

y:=b;

elsif

(sel="010") then

y:=c;

elsif

(sel="011") then

y:=d;

elsif
(sel="100") then

y:=e;

elsif

(sel="101") then

y:=f; elsif

(sel="110") then

y:=g; else

y:=h;

end if;

output <= y;

end process;

end behave;
Multiplexer 8to1dataflow modeling using Verilog.

Verilog Program

module mux8to1(I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2,y);

input I0,I1,I2,I3,I4,I5,I6,I7,s0,s1,s2;

output y;

assign y = (~ s2 & ~ s1 & ~ s0 &I0 ) |

(~ s2 & ~ s1 & s0 & I1 ) |

(~ s2 & s1 & ~ s0 & I2 ) |

(~ s2 & s1 & s0 & I3 ) |

( s2 & ~ s1 & ~ s0 & I4 ) |

( s2 & ~ s1 & s0 & I5 ) |

( s2 & s1 & ~ s0 & I6 ) |

( s2 & s1 & s0 & I7 );

endmodule
 4) 8 to 1 multiplexer in behavioural modeling.

Verilog Program

module mux8to1(I,sel,y);

input [7:0]I;

input [2:0]sel;

output reg y;

always@(I,sel)

begin

if(sel=="000") y=I[0];

else if (sel=="001") y=I[1];

else if (sel=="010") y=I[2];

else if (sel=="011") y=I[3];

else if (sel=="100") y=I[4];

else if (sel=="101") y=I[5];

else if (sel=="110") y=I[6];

else

y=I[7];

end

endmodule
 c) 4 bit binary to grey converter

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity bin2_gray is

port(a:in std_logic_vector(3 downto 0);

o:out std_logic_vector(3 downto 0));

end bin2_gray;

architecture behave of bin2_gray is

begin

process(a)

begin

o(3)<= a(3);

o(2)<= a(3) xor a(2);

o(1)<= a(2) xor a(1);

o(0)<= a(1) xor a(0);

end process;

end behave;
Verilog Program

module bin_grey(a,o);

input [3:0] a;

output [3:0] o;

reg [3:0] o;

always @ (a)

begin

o[3] = a[3];

o[2] = (a[3]^a[2]);

o[1] = (a[2]^a[1]);

o[0] = (a[1]^a[0]);

end

endmodule
d) 4 bit comparator in dataflow modeling

VHDL Program

entity com_pr is
Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);
aeqb : out STD_LOGIC;
agtb : out STD_LOGIC;
altb : out STD_LOGIC);
end com_pr;

architecture Behavioral of com_pr is

begin
aeqb <= (not a(1) and not a(0) and not b(1) and not b(0)) or
(not a(1) and a(0) and not b(1) and b(0)) or
(a(1) and not a(0) and b(1) and not b(0)) or
(a(1) and a(0) and b(1) and b(0));

altb <= (not a(1) and not a(0)) or

(not a(1) and a(0) and b(1)) or
(a(1) and not a(0) and b(1) and b(0));

agtb <= (not a(1) and a(0) and not b(1) and not b(0)) or
(a(1) and not a(0) and not b(1)) or
(a(1) and a(0));

end Behavioral;
e) 4 bit comparator in behavioural modeling

VHDL Program

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity comparator is

port(a,b:in std_logic_vector(3 downto 0);

altb,aeqb,agtb:out std_logic);

end comparator;

architecture behave of comparator is

begin

process(a,b)

begin

if(a > b)then

altb <='0';

aeqb<='0';

agtb<='1';

elsif

(a=b)then

altb <='0';

aeqb<='1';

agtb<='0';

else
altb <='1';

aeqb<='0';

agtb<='0';

end if;

end process;

end behave;
 3. Write a HDL code to describe the functions of a Full Adder using

three modeling styles

VHDL Program

a) Dataflow modeling

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity fa_ader is
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end fa_ader;
architecture behave of fa_ader is
signal q,l,n,p: bit;
begin
q<=a xor b;
l<=a and b;
n<=b and c;
p<=c and a;
sum<=q xor c;
carry<=l xor n xor p;
end behave;
b) Behavioral modeling

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity full_adder is

port(a,b,cin:in bit;

sum,carry:out bit);

end full_adder;

architecture behave of full_adder is

begin

process(a,b,cin)

variable s,c:bit;

begin

if(cin='0' and a='0' and b='0') then

s:='0'; c:='0';

elsif(cin='0' and a='0' and b='1') then

s:='1'; c:='0';

elsif(cin='0' and a='1' and b='0') then

s:='1'; c:='0';

elsif(cin='0' and a='1' and b='1') then

s:='0'; c:='1';

elsif(cin='1' and a='0' and b='0') then

s:='1'; c:='0';
elsif (cin='1' and a='0' and b='1') then

s:='0'; c:='1';

elsif (cin='1' and a='1' and b='0') then

s:='0'; c:='1';

else

s:='1'; c:='1';

end if;

sum <= s;

carry <=c;

end process;

end behave;
c) Structural modeling.

I. entity xrgate is
Port ( j,k : in STD_LOGIC;
l : out STD_LOGIC);
end xrgate;

architecture Behavioral of xrgate is

begin
l <= j xor k;
end Behavioral;

I. entity angate is
Port ( p,q : in STD_LOGIC;
r : out STD_LOGIC);
end angate;

architecture Behavioral of angate is

begin
r <= p and q;
end Behavioral;

II. entity org is

Port ( p,q : in STD_LOGIC;
r : out STD_LOGIC);
end org;

architecture Behavioral of org is

begin
r <= p or q;
end Behavioral;

Add above three sub modules in to main program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ader_struct is
Port ( a,b,cin : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end ader_struct;

architecture Behavioral of ader_struct is

component angate is
Port ( p,q : in STD_LOGIC;
r : out STD_LOGIC);
end component;

component org is
Port ( p,q : in STD_LOGIC;
r : out STD_LOGIC);
end component;

component xrgate is
Port ( j,k : in STD_LOGIC;
l : out STD_LOGIC);
end component;

signal m,n,o:STD_LOGIC;

begin

STR1 : xrgate port map(a,b,m);

STR2 : xrgate port map(m,cin,sum);

STR3 : angate port map(a,b,n);

STR4 : angate port map(m,cin,o);

STR5 : org port map(o,n,carry);

end Behavioral;
 4. Write a model for 32 bit ALU to perform according to given table below

en Sel Arithmetic function Logic function

0 000 Ain

00 001 Ain – 1

0 010 1 Ain + 1

0 011 Bin

0 100 Bin – 1

0 101 Bin + 1

0 110 Ain - Bin

0 111 Ain + Bin

1 000 Not Ain

1 001 Not Bin

1 010 Ain or Bin

1 011 Ain and Bin

1 100 Ain nor Bin

1 101 Ain nand Bin

1 110 Ain xor Bin

1 111 Ain xnor Bin

Arithmetic function program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ari_thop is

port ( a,b : in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

arith_out : out STD_LOGIC_VECTOR (31 downto 0));

end ari_thop;

architecture Behavioral of ari_thop is

begin

arith_out <= a when sel=000 else

a-1 when sel=001 else

a+1 when sel=010 else

b when sel=011 else

b-1 when sel=100 else

b+1 when sel=101 else

a-b when sel=110 else

a+b ;

end Behavioral;

Logic function program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logic_op is

port ( p,q : in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

logic_out : out STD_LOGIC_VECTOR (31 downto 0));

end logic_op;

architecture Behavioral of logic_op is

begin

logic_out <= not p when sel=000 else

not q when sel=001 else

p or q when sel=010 else

p and q when sel=011 else

p xor q when sel=100 else

p nand q when sel=101 else

p nor q when sel=110 else

p xnor q;

end Behavioral;

2 to 1 mux
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mx2_1pro is

Port (x,y : in STD_LOGIC_VECTOR (31 downto 0);

s : in STD_LOGIC;

z : out STD_LOGIC_VECTOR (31 downto 0));

end mx2_1pro;

architecture Behavioral of mx2_1pro is

begin

z <= x when (s='0') else

y;

end Behavioral;

To design ALU combine above three programmes using structural modeling.

Main 32 bit Arithmetic Logic Unit

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU_MAIN is

Port ( Ain,bin : in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

en : in STD_LOGIC;

Alu_output : out STD_LOGIC_VECTOR (31 downto 0));

end ALU_MAIN;

architecture Behavioral of ALU_MAIN is

component ari_thop is

Port ( a,b : in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

arith_out : out STD_LOGIC_VECTOR (31 downto 0));

end component;

component logic_op is

Port ( p,q: in STD_LOGIC_VECTOR (31 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

logic_out : out STD_LOGIC_VECTOR (31 downto 0));

end component;

component mx2_1pro is
 Port (x,y : in STD_LOGIC_VECTOR (31 downto 0);

s : in STD_LOGIC;

z : out STD_LOGIC_VECTOR (31 downto 0));

end component;

signal ar_1,log_2:STD_LOGIC_VECTOR (31 downto 0);

begin

ALU1 : ari_thop port map(Ain,bin,sel,ar_1);

ALU2 : logic_op port map(Ain,bin,sel,log_2);

ALU3 : mx2_1pro port map(ar_1,log_2,en,Alu_output);

end Behavioral;

5. develop the HDL code for the following flip-flops, SR, JK, D, T
SR flip-flop

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs_ff is

port(r,s,clk : in std_logic;

q : inout std_logic:='0';

qbar : inout std_logic:='1');

end rs_ff;

architecture flip of rs_ff is

signal m:std_logic:='0';

signal n:std_logic:='1';

begin

m <= not (s and clk);

n <= not (r and clk);

q <= m nand qbar;

qbar <= n nand q;

end flip;

MSJK flip-flop
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkff is

port(j,k,clk,rst:in bit;

q:out bit; --default value is '0'

qbar:out bit:='1'); --compliment of the output

end jkff;

architecture behave of jkff is

begin

process(rst,clk,j,k)

variable a:bit:='0';

begin

if (rst='1') then

a :='0';

elsif(clk='1' and clk'event) then

if (j='0' and k='0') then

a := a;

elsif

(j='0' and k='1') then

a := '0';

elsif (j='1' and k='0') then

a := '1';

else

a := not a;

end if;

end if;

q <= a;

qbar <= not a;

end process;

end behave;

D-Flip-flop
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DFF is

port (

clk: in STD_LOGIC; --Global Clock as Input

d: in STD_LOGIC; -- Single bit Input

q: out STD_LOGIC ); -- Single bit output

end DFF;

architecture d_ff_arch of DFF is

begin

process(clk)

begin

if(clk'event and clk='1')then

q<=d;

end if;

end process;

end d_ff_arch;

T-Flip-flop
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TFF is

port ( T: in STD_LOGIC; -- Input T

clk: in STD_LOGIC; -- Global Clock Signal

q: out STD_LOGIC ); -- Q Output

end TFF;

architecture t_ff_arch of TFF is

begin

process(clk)

begin

if(clk'event and clk='1')then

q<=not t;

end if;

end process;

end t_ff_arch;

6) Design 4 bit binary, BCD counters (synchronous reset and

 Asynchronous reset) and “any sequence counters

a) 4-bit synchronous counter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sync_counter is

port( CLK: in STD_LOGIC; -- GLOBAL CLOCK SIGNAL

RESET: in STD_LOGIC; -- Global Reset Signal

COUNT: out STD_LOGIC_VECTOR( 3 DOWNTO 0)); --Counter Output

end sync_counter;

architecture counter_arch of sync_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);

begin

process (CLK)

begin

if CLK='1' and CLK'event then

if RESET='1' then --Synchronous reset

TEMP <= (OTHERS=>'0');

ELSE

TEMP <= TEMP + 1;

end if;

COUNT<= TEMP;

end if;

end process;

end counter_arch;

b) 4-bit asynchronous counter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity async_counter is

port( CLK: in STD_LOGIC; -- GLOBAL CLOCK SIGNAL

RESET: in STD_LOGIC; -- Global Reset Signal

COUNT: out STD_LOGIC_VECTOR( 3 DOWNTO 0)); --Counter Output

end async_counter;

architecture counter_arch of async_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);

begin

process (CLK,RESET)

begin

if RESET='1' then --asynchronous reset

TEMP <= (OTHERS=>'0');

elsif CLK='1' and CLK'event then

TEMP <= TEMP + 1;

COUNT<= TEMP;

end if;

end process;

end counter_arch;