Getting Started with SystemC

UVM
Verification in SystemC Perspective

Puneet Goel
Coverify Systems Technology

April 2012

Co v e r i f y

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Introduction
I

UVM stands for Universal Verification

Methodology

UVM is the Accellera approved standard

methodology for verification

UVM is primarily coded in SystemVerilog

In November 2011, Cadence released UVM
Multi-language package on UVM website
http://uvmworld.com

The package contains a partial port of UVM

Library in SystemC and e

In Feburary 2012, Mentor Graphics released

opensource implementation of uvm::connect,
and named the library UVMC
Both UVM-ML and UVMC have been released
under Apache License

Getting Started with SystemC UVM

Co v e r i f y
2 / 22

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Assertions

Functional
Coverage

Testcase

Signal
Layer

Command Functional Sequence

Layer
Layer
Layer

Test
Layer

UVM Testbench

Collector

Design
Under Test

Figure: UVM Testbench Infrastructure

Co v e r i f y
Getting Started with SystemC UVM

3 / 22

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Assertions

Functional
Coverage

Testcase

Signal
Layer

Command Functional Sequence

Layer
Layer
Layer

Test
Layer

SystemC UVM Testbench

Collector

Design
Under Test

Figure: Currently Supported by SystemC UVM

Co v e r i f y
Getting Started with SystemC UVM

4 / 22

Testcase

Constrained
Randomization

Checker

Transactor

Driver

Functional
Coverage

Sequencer

Signal
Layer

Command Functional Sequence

Layer
Layer
Layer

Test
Layer

SystemC UVM Testbench

Monitor

Collector

Assertions

Collector

Design
Under Test

Figure: Currently Supported by SystemC UVM

Co v e r i f y
Getting Started with SystemC UVM

4 / 22

Register
Abstraction Layer

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Assertions

Functional
Coverage

Testcase

Signal
Layer

Command Functional Sequence

Layer
Layer
Layer

Test
Layer

SystemC UVM Testbench

Collector

Design
Under Test

Figure: Currently Supported by SystemC UVM

Co v e r i f y
Getting Started with SystemC UVM

4 / 22

In this section . . .

SystemC Perspective
Why SystemC for Verification
UVM for SystemC

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

5 / 22

Why SystemC?

A couple of questions that obviously prop are:

I Is not verification meant to be done using HVLs like
Specman/Vera/SystemVerilog etc?
I Is not UVM primarily coded in SystemVerilog?
I What advantage does SystemC has over SystemVerilog?

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

6 / 22

Why SystemC?

A couple of questions that obviously prop are:

I Is not verification meant to be done using HVLs like
Specman/Vera/SystemVerilog etc?
I Is not UVM primarily coded in SystemVerilog?
I What advantage does SystemC has over SystemVerilog?

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

6 / 22

Why SystemC?

A couple of questions that obviously prop are:

I Is not verification meant to be done using HVLs like
Specman/Vera/SystemVerilog etc?
I Is not UVM primarily coded in SystemVerilog?
I What advantage does SystemC has over SystemVerilog?

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

6 / 22

SystemC model used as golden

reference model for verification

Testcase

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Functional
Coverage

Command Functional Sequence

Layer
Layer
Layer

Verification of ESL components

coded in SystemC using
SystemVerilog based testbenches
Using SystemC Driver and
Monitor components in
SystemVerilog testbench

Signal
Layer

Test
Layer

SystemC UVM Use Cases

Collector

Assertions

Design
Under Test

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

7 / 22

SystemC model used as golden

reference model for verification

Testcase

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Functional
Coverage

Command Functional Sequence

Layer
Layer
Layer

Verification of ESL components

coded in SystemC using
SystemVerilog based testbenches
Using SystemC Driver and
Monitor components in
SystemVerilog testbench

Signal
Layer

Test
Layer

SystemC UVM Use Cases

Collector

Assertions

Design
Under Test

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

7 / 22

SystemC model used as golden

reference model for verification

Testcase

Sequencer

Checker

Transactor

Monitor

Driver

Collector

Functional
Coverage

Command Functional Sequence

Layer
Layer
Layer

Verification of ESL components

coded in SystemC using
SystemVerilog based testbenches
Using SystemC Driver and
Monitor components in
SystemVerilog testbench

Signal
Layer

Test
Layer

SystemC UVM Use Cases

Collector

Assertions

Design
Under Test

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

7 / 22

SystemC for coding Reference Model

I

SystemVerilog is a Hardware Design and Verification Language

I
I

Often your DUT (or a part of it) would be coded using verilog
Coding reference model in the same language as the language in which
your design has been coded is often a bad idea

When designers and verification

engineers use same language,
there is a risk that they might
share code

Or might make same mistakes

they would have the same set of
language gotchas to deal with

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

8 / 22

SystemC for coding Reference Model

I

SystemVerilog is a Hardware Design and Verification Language

I
I

Often your DUT (or a part of it) would be coded using verilog
Coding reference model in the same language as the language in which
your design has been coded is often a bad idea

When designers and verification

engineers use same language,
there is a risk that they might
share code

Or might make same mistakes

they would have the same set of
language gotchas to deal with

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

8 / 22

SystemC for coding Reference Model

I

SystemVerilog is a Hardware Design and Verification Language

I
I

Often your DUT (or a part of it) would be coded using verilog
Coding reference model in the same language as the language in which
your design has been coded is often a bad idea

When designers and verification

engineers use same language,
there is a risk that they might
share code

Or might make same mistakes

they would have the same set of
language gotchas to deal with

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

8 / 22

SystemC for coding Reference Model

I

SystemVerilog is a Hardware Design and Verification Language

I
I

Often your DUT (or a part of it) would be coded using verilog
Coding reference model in the same language as the language in which
your design has been coded is often a bad idea

When designers and verification

engineers use same language,
there is a risk that they might
share code

Or might make same mistakes

they would have the same set of
language gotchas to deal with

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

8 / 22

SystemC for coding Reference Model

I

SystemVerilog is a Hardware Design and Verification Language

I
I

Often your DUT (or a part of it) would be coded using verilog
Coding reference model in the same language as the language in which
your design has been coded is often a bad idea

When designers and verification

engineers use same language,
there is a risk that they might
share code

Or might make same mistakes

they would have the same set of
language gotchas to deal with

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

8 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

Generic Library

I
I

Though SystemVerilog supports parameterized classes, it does not

support function and operator overloading
As a result, SystemVerilog lacks a generic algorithmic library
I

For example if you develop a sort function in systemverilog that works for
builtin number types, you can not generalize this function to work on
user-defined data types

In comparison SystemC, since it is built over C++, has generic libraries

such as STL and boost
I
I

These libraries come in handy when you are modeling at behavioral level
Also since C++ has a much bigger user-base, these libraries are well-tested
and therefor are ideal for creating reference models

Co v e r i f y
Getting Started with SystemC UVM

SystemC Perspective

9 / 22

In this section . . .

SystemC Perspective
UVM for SystemC
UVM Constructs

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

10 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

SystemC UVM Features

Configuration Global configuration object that records configuration for UVM
components even before they are constructed. Helpful for
creating object specific behaviour.
Factory Implementation of Abstract and Concrete factories in C++.
Useful for transaction and component creation.
Packing Packer class implementation. Enables passing data
transactions between SystemC and SystemVerilog.
Phasing Enables synchronized build, configure, connect, run, report
operations.
Connect Enables connections between SystemVerilog and SystemC
components.
Conversion Package for conversion between SystemC and SystemVerilog
standard data types.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

11 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I
I

UVM Components as well as SystemC models tend to be hierarchical in

nature
Different components in a hierarchy are bound by ports and channels
I
I

Ports and Channels form the interface of a component (or module)

Any other component (or module) that wants to access a given module,
does it through the interface

Such structural models give rise to rigidity

I

A change in one module, disturbs all the modules that are bound to this
module

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

12 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

component
A
component
B
component
C

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

component
A
component
B
component
C

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

component
A
component
B
component
C

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

I

In UVM testbenches and in SystemC models, the problem is compunded

by availability of various forms of comonents modeled at different
abstraction levels
For example various models may be available for a given component,
including:

untimed
loosely time
cycle accurate

a combination

component
A
component
B
component
C

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

13 / 22

Harnessing the UVM Factory

The OOP paradigm comes to our rescue here, in form of polymorphism

OOP principles tell us not

to program to the
implementation

Instead program to the

interfaces, we are told

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

14 / 22

Harnessing the UVM Factory

I

The OOP paradigm comes to our rescue here, in form of polymorphism

Component A Package

OOP principles tell us not

to program to the
implementation
Instead program to the
interfaces, we are told

UVM
component A

component A
service

Component B Package
UVM
UVM
UVM
component
B
component
B
component
B

component B
service

Component C Package
UVM
UVM
UVM
component
C
component
B
component
B

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

14 / 22

Harnessing the UVM Factory

I

The OOP paradigm comes to our rescue here, in form of polymorphism

Component A Package

OOP principles tell us not

to program to the
implementation
Instead program to the
interfaces, we are told

UVM
component A

component A
service

Component B Package
UVM
UVM
UVM
component
B
component
B
component
B

component B
service

Component C Package
UVM
UVM
UVM
component
C
component
B
component
B

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

14 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
I

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
I

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
I

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
I

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
I

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp B
Cycle Accurate

Comp B

Comp A

<<interface>>

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Comp B

Loosely Timed

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp B
Cycle Accurate

Comp B

Comp A

<<interface>>

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Comp B

Loosely Timed

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

Logical application of OOP paradigm makes our code independent of the

implementation details instead the compenents are now bound to an
interface (virtual base class)

Polymorphism ROCKS, but whoa, does it really work all the time:
<<creates>>

Comp B
Cycle Accurate

Comp B

Comp A

<<interface>>

While all other methods (class

functions) can be made virtual, the
constructor can not be

As a result, at the time of creating the

component, a particular
implementation has to be specified

Object generation spoils much of what

polymorphism had to offer

Comp B

Loosely Timed

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

15 / 22

Harnessing the UVM Factory

I

This is exactly where UVM Factory comes to our rescue:

UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

UVM (concrete) Factory is a global

singleton object
Base classes as well as derived classes
are registered with the global factory
Configuration interface is provided for any
base class, so that when you create an
object of the base class, the actual object
created is for a derived class as per the
configuration

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

16 / 22

Harnessing the UVM Factory

I

This is exactly where UVM Factory comes to our rescue:

UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

UVM (concrete) Factory is a global

singleton object
Base classes as well as derived classes
are registered with the global factory
Configuration interface is provided for any
base class, so that when you create an
object of the base class, the actual object
created is for a derived class as per the
configuration

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

16 / 22

Harnessing the UVM Factory

I

This is exactly where UVM Factory comes to our rescue:

UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

UVM (concrete) Factory is a global

singleton object
Base classes as well as derived classes
are registered with the global factory
Configuration interface is provided for any
base class, so that when you create an
object of the base class, the actual object
created is for a derived class as per the
configuration

Comp A
<<interface>>

UVM Factory
+ create()

UVM Factory

<<interface>>

Comp B

Comp B

Comp B

Loosely Timed

Cycle Accurate

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

16 / 22

Harnessing the UVM Factory

I

This is exactly where UVM Factory comes to our rescue:

UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

UVM (concrete) Factory is a global

singleton object
Base classes as well as derived classes
are registered with the global factory
Configuration interface is provided for any
base class, so that when you create an
object of the base class, the actual object
created is for a derived class as per the
configuration

Comp A
<<interface>>

UVM Factory
+ create()

UVM Factory

<<interface>>

Comp B

Comp B

Comp B

Loosely Timed

Cycle Accurate

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

16 / 22

Harnessing the UVM Factory

I

This is exactly where UVM Factory comes to our rescue:

UVM Factory is an implementation of the popular generational design

patterns Abstract Factory and Concrete Factory

UVM (concrete) Factory is a global

singleton object
Base classes as well as derived classes
are registered with the global factory
Configuration interface is provided for any
base class, so that when you create an
object of the base class, the actual object
created is for a derived class as per the
configuration

Comp A
<<interface>>

UVM Factory
+ create()

UVM Factory

<<interface>>

Comp B

Comp B

Comp B

Loosely Timed

Cycle Accurate

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

16 / 22

UVM Phases
SystemC has only a few phases. In contrast, UVM has a very elaborate phase
sequence.
VerilogElaboration
End of Elaboration
Start of Simulation
UVM Build Phase
UVM Connect Phase

SystemC
Elaboration

Note that Start of Elaboration and

Start of Simulation etc are PLI
hooks in Verilog and similarly are
function hooks in SystemC

The Build and Connect phase in

UVM happen at ZERO simulation
time

End of Elaboration
Start of Simulation

UVM Run Phase

Simulation Run

UVM Extract Phase

UVM Check Phase

End of Simulation

UVM Report Phase

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

17 / 22

UVM Phases
SystemC has only a few phases. In contrast, UVM has a very elaborate phase
sequence.
VerilogElaboration
End of Elaboration
Start of Simulation
UVM Build Phase
UVM Connect Phase

SystemC
Elaboration

Note that Start of Elaboration and

Start of Simulation etc are PLI
hooks in Verilog and similarly are
function hooks in SystemC

The Build and Connect phase in

UVM happen at ZERO simulation
time

End of Elaboration
Start of Simulation

UVM Run Phase

Simulation Run

UVM Extract Phase

UVM Check Phase

End of Simulation

UVM Report Phase

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

17 / 22

Configuring a Build

Not all the instances of a class

(UVM Component) may be exactly
same in behaviour
There may be a need to configure
a UVM Component
Often, it might be useful to build a
UVM component while taking
some configuration parameters
into account

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Processor
Master

Global
Memory

Routing
Node

Global
IO

Routing
Node

Global
IO

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Routing
Node

Processor
Master

Routing
Node

Figure: Asymmetric Architecture

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

18 / 22

Configuring a Build

Not all the instances of a class

(UVM Component) may be exactly
same in behaviour
There may be a need to configure
a UVM Component
Often, it might be useful to build a
UVM component while taking
some configuration parameters
into account

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Processor
Master

Global
Memory

Routing
Node

Global
IO

Routing
Node

Global
IO

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Routing
Node

Processor
Master

Routing
Node

Figure: Asymmetric Architecture

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

18 / 22

Configuring a Build

Not all the instances of a class

(UVM Component) may be exactly
same in behaviour
There may be a need to configure
a UVM Component
Often, it might be useful to build a
UVM component while taking
some configuration parameters
into account

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Processor
Master

Global
Memory

Routing
Node

Global
IO

Routing
Node

Global
IO

Processor
Master

Routing
Node

Processor
Master

Routing
Node

Routing
Node

Processor
Master

Routing
Node

Figure: Asymmetric Architecture

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

18 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

Configuring the Build UVM Way

The Configure object provided by UVM is useful for providing configuration
parameters in the build phase
I The parameters are tied with the hierarchical name of the component
being built. This is useful for enabling instance-specific custom behaviour
for a component.
Caveat Note that the configuration object needs the same fields on pthe
configure and component side.
I This results in a strong binding (in the software sense).
I Sometimes it results in confusing situations (because of
typos in the configure parameters).

Use with care

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

19 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Transactions
I

UVM-SC library provides a base class for creating a transaction (called

sequence item in UVM)

The UVM-SC implementation lacks CPP macros to automatically create

virtual methods for print, pack, unpack, copy and compare operations
UVM-SC makes it mendatory for the user to implement these functions

I
I

A transaction class can be registered with the UVM factory, making it

possible to generate transaction objects using the factory

UVM-SC depends on the pack/unpack operations to send transactions

across the language boundaries

A user must make sure that pack/unpack methods for the transaction
class in SystemC and SystemVerilog remain in sync
Caveat When you pack data in SystemVerilog or in SystemC, you loose
the control bits for any 4-valued logic data.

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

20 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

UVM Connect Library

I

The UVM Connect package from Mentor Graphics is built on top of

UVM-SC package by Cadence

It provides an opensource implementation for connecting SystemVerilog

and SystemC ports

Also implements conversion between standard SystemC and

SystemVerilog data types
UVMC package does not require you to create a UVM transaction on the
SystemC side

Instead it provides macros to automatically define the pack/unpack

functionality on SystemC side
Since these macros define functions (not class methods) for the
pack/unpack functionality, UVMC does not bind your SystemC transaction
class to any base class

Co v e r i f y
Getting Started with SystemC UVM

UVM for SystemC

21 / 22

Thank You!

Co v e r i f y