Synthesizable Coding of Verilog

REF: Verilog Training Manual, CIC, July, 2008 Reuse Methodology Manual For System-ON-A-Chip Design, Third Edition 2002 Logic Synthesis with Design Complier, CIC , July, 2008

Speaker: Y. X. Chen
Advanced Reliable Systems (ARES) Lab.

Nov. 2012
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: Synthesizable Verilog & Coding
Synthesizable coding style in Verilog Syntax check with nLint

LAB1-simple 8-bit microprocessorVerilog code

:RTL codingnLintcode :RTL netlistsimulation

Advanced Reliable Systems (ARES) Lab.

Outline
Basic of Logic Synthesis Concept Basic Concept of Verilog HDL Synthesizable Verilog LAB 1-1: Design Rule Check with nLint Tips for Verilog Design LAB 1-2: RTL Simulation

Advanced Reliable Systems (ARES) Lab.

Basic Concept of the Synthesis

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Cell-Based Design Flow

Spec. System Level
MATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim) Memory Generator

RTL Level

Verilog/ VHDL

NC-Verilog/ ModelSim Debussy (Verdi)/ VCS Physical Compiler/ Magma Blast Fusion Design/ Power Compiler DFT Compiler/ TetraMAX NC-Verilog/ ModelSim Debussy (Verdi)/ VCS SOC Encounter/ Astro GDS II DRC/ LVS (Calibre)
PVS: Calibre xRC/ NanoSim (Time/ Power Mill)

Syntest

Logic Synthesis Design for Test Gate Level

Conformal/ Formality

Layout Level Post-Layout Verification

Tape Out
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What is Synthesis
Synthesis = translation + optimization + mapping
if(high_bits == 2b10)begin residue = state_table[i]; end else begin residue = 16h0000; end

Translate (HDL Compiler)

HDL Source (RTL)

No Timing Info. Optimize + Mapping (HDL Compiler)

Generic Boolean (GTECT)

Timing Info. The synthesis is constraint driven and technology independent !!

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Target Technology
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Notice Before Synthesis

Area

Your RTL design

Functional verification by some high-level language Coding style checking (i.e. n-Lint)

Better
Cycle Time

Also, the code coverage of your test benches should be verified (i.e. VN) Good coding style will reduce most hazards while synthesis Better optimization process results in better circuit performance Easy debugging after synthesis

Constraints
The area and timing of your circuit are mainly determined by your circuit architecture and coding style There is always a trade-off between the circuit timing and area In fact, a super tight timing constraint may be worked while synthesis, but failed in the Place & Route (P&R) procedure
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Basic Concept of Verilog HDL

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Verilog Model
Key features of Verilog
Supports various level of abstraction
Switch level model or transistor level model Gate level model Data flow model or register transfer model Behavioral model

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Register Transfer Level (RTL)

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Gate Level Model

Model consists of basic logic
Ex. AND, NAND, OR, NOR, XOR, NOT, etc.

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Verilog Module
/* This is sample code. The function is ALU. */ module ALU(a,b,sel,out); input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select reg [7:0]out; wire always@(...)begin end endmodule

module module_name(port_names); Port declaration Data type declaration Task & function declaration Module functionality or structure Timing Specification endmodule

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Verilog Syntax
Verilog consists of a series token
Comment: //, /* */ operators: unary, binary, ternary
A=~B; A=B&C; C=SEL?A:B;

Numbers: size, unsized

Sized: 4b0010, 8ha

Identifiers: $, #, etc. Keywords

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Verilog Syntax (Contd)

always@ statement
Blocking Non-blocking
always @ (posedge clk) begin x_temp<=x; end always @ (a or x_temp)begin if (a) begin x= x_temp+1b1; end else begin x= x_temp; end

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Verilog Syntax (Contd)

Case statement If-else statement
always @ (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; endcase end always @ (a or x_temp)begin if (a) begin x= x_temp+1b1; end else begin x= x_temp; end
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Connection Manners

net/register net net/register input net output inout net net

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Synthesizable Verilog

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Importance of Coding Style

Make sure your code is readable, modifiable, and reusable Good coding style helps to achieve better results in synthesis and simulation

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Concept of Clocks and Reset

Synchronous
D Q clk CBL D Q clk

Mixed Clock Edges

D Q CBL D Q

Gated Clocks Combination Feedback

CBL clk D Q D Q

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Asynchronous and Synchronous Reset

Synchronous reset
always@(posedge clock)begin if (rst) begin . end end

Asynchronous reset
always@(posedge clock or negedge reset) if (!rst) begin end end
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Synthesizable Verilog
Not all kinds of Verilog constructs can be synthesized Only a subset of Verilog constructs can be synthesized and the code containing only this subset is synthesizable

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Synthesizable Verilog (Cont)

Verilog Basis
parameter declarations wire, wand, wor declarations reg declarations input, output, inout continuous assignment module instructions gate instructions always blocks task statement function definitions for, while loop
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Synthesizable Verilog primitives cells

and, or, not, nand, nor, xor, xnor bufif0, bufif1, notif0, notif1

Can not use for Synthesis

=== !== / (division) % (modulus) delay Initial repeat forever wait fork join event
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Synthesizable Verilog (Cont)

Operators
Concatenation ( { }, {{}} ) Unary reduction ( !, ~, &, |, ^ ) 2s complement arithmetic ( +, -, *) Logic shift ( >>, << ) Relational ( >, <, >=, <= ) Equality ( ==, != ) Binary bit-wise ( &, |, ^, ~^ ) Logical ( &&, || ) Conditional ( ?: )

precedence
highest

lowest

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Coding for Synthesis

Combinational Blocks
always @ (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; endcase end always @ (a or x_temp)begin if (a) begin x= x_temp+1b1; end else begin x= x_temp; end
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Sequential Blocks
always @ (posedge clk )begin if (a) begin z<=1b1; end else begin z<=1b0; end end

Coding for Synthesis (Cont)

Avoid Combinational Feedback
always @ (a or x)begin if (a) begin x= x+1b1; end else begin x= x; end always @ (posedge clk) begin x_temp<=x; end always @ (a or x_temp)begin if (a) begin x= x_temp+1b1; end else begin x= x_temp; end

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Coding for Synthesis (Cont)

Blocking Assignment
always @ (posedge clk )begin b=a; c=b; end Just like a=c; a D Q b c a

Non-Blocking Assignment
always @ (posedge clk )begin b<=a; c<=b; end Just like shift register D Q b D Q c

clk

clk

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Coding for Synthesis (Cont)

Avoid Latches
always @ (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; endcase end always @ (d)begin if (a) begin ............ end else begin ........... end end
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always @ (d) begin x=1b0; z=1b0; case (d) 2'b00: begin z=1'b1; x=1b1; end 2'b01: begin z=1'b0; end default : begin z=1'b0; end endcase end always @ (posedge clk )begin if (a) begin z<=1b1; end else begin z<=1b0; end end
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Coding for Synthesis (Cont)

Sensitivity List
always @ (d) begin case (d) 2'b00: z=1'b1; 2'b01: z=1'b0; default : z=1'b0; endcase end always @ (a or b or c or d)begin if (a) begin ............ end else begin if (b)begin z=c; end else begin z=d; end end end

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Coding for Synthesis (Cont)

Case statements
always @ ( sel or a or b or c or d)begin case (sel) 2'b00:out=a; 2'b01:out=b; 2'b10:out=c; 2'b11:out=d; endcase end a b c d 00 01 10 11 sel
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if else statements
always @ ( sel or a or b or c or d) begin if (sel==2'b00) out=a; else if (sel==2'b01) out=b; else if (sel==2'b10) out=c; else out=d; end sel d c b a 0 1

out

0 1

0 1

out

Lab 1-1 Design Rule Check with nLint

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Design Rule Check

Use nLint tool (include by Debussy) and the Verilog Coding Guideline to check your design and modify parts of code to match the coding guidelines

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Start nLint
Unix% nLint gui &

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Load Verilog Code (1/2)

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Load Verilog Code (2/2)

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Run nLint Check

Compile

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nLint Check Result (1/2)

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nLint Check Results (2/2)

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Lab Time

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11/28
: Synthesizable Verilog & Coding
Tips for Verilog Design RTL simulation Waveform viewer nWave / Debussy

LAB1-simple 8-bit microprocessorVerilog code

:RTL codingnLintcode :RTL netlistsimulation

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Outline
Basic of Logic Synthesis Concept Basic Concept of Verilog HDL Synthesizable Verilog LAB 1-1: Design Rule Check with nLint Tips for Verilog Design LAB 1-2: RTL Simulation

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Tips for Verilog Design

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Pre-RTL Preparation Checklist

Communicate design issues with your team
Naming conventions, revision control, directory tree and other design organizations

Have a specification for your design

Everyone should have a specification before they start coding

Design partition
Follow the specifications recommendations for partition Break the design into major function blocks

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RTL Coding Style

Create a block level drawing of your design before you begin coding
Draw a block diagram of the function and sub-function of your design

Always think of the poor guy who has to read your RTL code
Correlate top to bottom in the RTL description with left to right in block diagram Comments and headers

Hierarchy design
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Basic Coding Practices

Naming Conventions
Use lowercase letters for all signal names, and port names, versus uppercase letters for names of constants and user-defined types Use meaningful names For active low signals, end the signal name with an underscore followed by a lowercase character (e.g., rst_ or rst_n) Recommend using bus[X:0] for multi-bit signals

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Basic Coding Practices (Cont)

Include Headers in Source Files and Comments

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Basic Coding Practices (Cont)

Indentation Port Maps and Generic Maps

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Basic Coding Practices (Cont)

Use Functions or Tasks
Which Instead of repeating the same sections of code

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Write Efficient HDL Code

Use parentheses control complex structure of a design Resource Sharing Scalable design and propagate constant value Use operator bit-width efficiently Timescale

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Use Parentheses Properly

out=a+b+c+d+e
a b c d e

out=((a+(b+c))+(d+e));
c b a d e

out out
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Resource Sharing
Operations can be shared if they lie in the same always blocks

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Scalable Design & Constant

parameter size=8; wire [3:0] a,b,c,d,e; assign a=size+2; assign b=a+1; assign c=d+e;

Constant Increaser Adder

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Use Operator Bit-width Efficiently

module fixed_multiplier(a,b,c); input [8:0] a, b; output [8:0] c; reg [15:0] tmp; reg [8:0] c; assign tmp = a*b; assign c = tmp(15,8); endmodule

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Timescale
`timescale: which declares the time unit and precision.
`timescale <time_unit> / <time_precision> e.g. : `timescale 1s/1ps, to advance 1 sec, the timewheel scans its queues 1012 times versus a `timescale 1s/1ms, where it only scans the queues 103 times.

The time_precision must be at least as precise as the time_unit. Keep precision as close in scale to the time units as is practical. If not specified, the simulator may assign a default timescale unit. The smallest precision of all the timescale directive determines the simulation time unit of the simulation.

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Omit for Synthesis

Omit the Wait for XX ns Statement
Do not use #XX;

Omit the ...After XX ns or Delay Statement

Do not use assign #XX Q=0;

Omit initial values

Do not use initial sum = 1b0;

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Non-Synthesizable Style
Either non-synthesizable or incorrect after synthesis initial block is forbidden (non-synthesizable) Multiple assignments (multiple driving sources) Mixed blocking and non-blocking assignment

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Summary
No initial in the RTL code Avoid unnecessary latches Avoid combinational feedback For sequential blocks, use non-blocking statement For combinational blocks, use blocking statements

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Lab 1-2 RTL Simulation

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Tools
Simulators
Verilog-XL, NC-Verilog, Altera Quartus, ModelSim and etc.

Synthesizers
Design vision, Ambit, and etc.

Debugger and verification tools

Debussy, nWave, nLint, and etc. nLint can check the correctness of your codes syntax

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Verilog Simulator

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Run Verilog Simulation(1/2)

Method 1:
unix% verilog alu.v t_alu.v unix% ncverilog +access+r alu.v t_alu.v Method 2: Using additional file alu.f alu.v t_alu.v unix% verilog -f alu.f unix% ncverilog +access+r -f alu.f

Method 3:
Using additional description `include module_file
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Run Verilog Simulation(2/2)

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Testbench
Compare this with your design
module testfixture; Declare signals Instantiate modules Applying stimulus Monitor signals endmodule

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FSDB File
Waveform file format Add commands in testbench
// testbench.v module (); initial begin $fsdbDumpfile(abcd.fsdb); $fsdbDumpvars; End endmodule

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Example of Testbench
//t_alu.v /* This is testbench of sample code. The function is ALU. */ module test_ALU; reg [7:0] A,B; reg[2:0]SEL; wire[7:0] OUT; ALU U0(.a(A),.b(B),.sel(SEL),.out(OUT)); always #5 B=~B; initial begin A=0;B=0;SEL=0; #10 A=0;SEL=1; #10 SEL=0; .. #10 SEL=1; #10 $finish; end initial begin $fsdbDumpfile(ALU.fsdb); $fsdbDumpvars; end endmodule

//alu.v /* This is sample code. The function is ALU. */ module ALU(a,b,sel,out); input [7:0] a,b; //Data in output[7:0]out; //Data out input [2:0]sel; //Control select reg [7:0]out; wire always@(...)begin end endmodule
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Debussy Getting Start

Using nWave or Debussy
unix% nWave& unix% debussy&

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Get Signals
Select Signal -> Get Signal

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Observe Waveform

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Change Radix

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Save Waveform

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LAB Time

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