PRRM ENGINEERING COLLEGE
SHABAD-509 217.
Course file
Class : II B.Tech.
Semester : I Semester.
Branch : Computer Science and Engineering.
Name of Faculty : V. Rajesh M.Tech.
Department : Electronics and Communication Engineering.
Designation : Asst. Professor.
Subject name : Digital Logic Design.
Subject code : 53024.
PRRM ENGINEERING COLLEGE
SHABAD-509217
Course file contents
Time Table Copy
Syllabus Copy
Academic Calendar Copy for Semester
Lesson Plan Sheets
Course Notes
Previous Question Papers-
i) Internal Unit Test Papers
ii) University External Examination Papers
Student Previous Marks Analysis Sheets
PRRM ENGINEERING COLEGE
SHABAD 509 217
Department of Electronics and Communication Engineering
Personal Time Table
Class : II B.Tech.
Semester : I-Semester.
Branch : Computer Science and Engineering.
Subject : Digital Logic Design.
Subject code : 07A4EC09.
Name of the Staff member : V. Rajesh M.Tech.
DAY I II II IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
PRRM ENGINEERING COLEGE
SHABAD 509 217
Department of Computer Science and Engineering
Time Table
Class : II B.Tech.
Semester : II Semester.
Branch : Computer Science and Engineering.
CSE-A
DAY I II II IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
CSE-B
DAY I II III IV V VI VII
MON
TUE
WED
THUR
FRI
SAT
Jawaharlal Nehru Technological University Hyderabad
II-year B.Tech CSE-I Sem L T/P/D C
4 1/-/- 3
DIGITAL LOGIC DESIGN (53024)
UNIT-I
BINARY SYSTEMS: Digital system, Binary number, Number base conversion, Octal and Hexadecimal
Numbers, complements, signed binary numbers, Binary storage and Registers.
UNIT-II
BOOLEAN ALGEBRA AND LOGIC GATES: Basic Definitions, Axiomatic definitions of Boolean
Algebra, basic theorems and properties of Boolean Algebra, Boolean functions canonical and standard
forms, other logical operation, Digital logic gates, integrated circuits.
UNIT-III
GATE-LEVEL MINIMIZATION: The map method, Four-variable map, Five- variable map, product of
sums simplification, Don’t care conditions, NAND and NOR implementation other Two-level
implementations, Exclusive-Or function, Hardware Description language (HDL).
UNIT-IV
COMBINATIONAL LOGIC: Combinational Circuits, Analysis procedure, Design procedure, Binary
Adder-Subtractor, Decimal Adder, Binary multiplier, magnitude comparator, Decoders, Encoders,
Multiplexers, HDL for Combinational circuits.
UNIT-V
SYNCHRONOUS SEQUENTIAL LOGIC: Sequential circuits, latch, Flip-Flops Analysis of clocked
sequential circuits, HDL for sequential circuits, State Reduction and Assignment, Design Procedure.
UNIT-VI
Registers, shift Registers, Ripple counters synchronous counters, other counters, HDL for Registers and
counters.
UNIT-VII
Introduction, Random-Access Memory, Memory Decoding, Error Detection and correction Read only
memory, Programmable logic Array programmable Array logic, Sequential Programmable Devices.
UNIT-VIII
ASYNCHRONOUS SEQUENTIAL LOGIC: Introduction, Analysis procedure, Circuits with latches,
Design Procedure, Reduction of state and Flow Tables, Race-Free state Assignment Hazards, Design
Example.
TEXT BOOKS:
1. Digital Design – Morris mano, PHI,3rd Edition, 2006.
2. Fundamentals of logic Design- charles h. Roth, Thomson publications 5 th Edition, 2004.
REFERANCES:
1. Switching & Finite Automata Theory –Zvi kohavi, TMH, 2nd edition.
2. Switching and Logic Design, C.V.S.Rao, Pearson Education
3. Digital Principles Design – Donald D. Givone, Tata McGraw Hill, Edition.
4. Fundamentals of Digital Logical & Micro Computer Design, 5 TH Edition, M Rafiquzzaman John
Wiley.
PRRM ENGINEERING COLLEGE
SHABAD-509 217.
Class: II B.Tech (CSE) I- Semester. Synopsis for: Digital Logic Design.
Lecturer: V. Rajesh M.Tech.
Required Starting &
No of Ending
Sl. No Unit-No. Contents Classes dates Remarks
1 Unit-I Binary Systems 8
2 Unit-II Boolean Algebra and 9
Logic Gates
3 Unit-III Gate Level Minimization 8
4 Unit-IV Combinational Logic 8
5 Unit-V Synchronous Sequential 8
Logic
6 Unit-VI Registers & Counter 7
7 Unit-VII Memory Devices 8
8 Unit-VIII Synchronous Sequential 8
Logic
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 1/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : I Department: ECE.
Designation: Asst. Prof.
Unit title: Binary Systems.
Objective: To brief study about Number system, number converstion.
S.No. Subject Topics Periods Reference material
1 Digital system & Binary number. 2 1
2 Number base conversion, Octal and 2
Hexadecimal Numbers. 1
3 Complements & signed binary 2
1
numbers.
4 Binary storage and Registers. 2 2
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1 to 3
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 4
Teaching aids: S.No.
1. O.H.P. 3&4
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 2/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : II Department: ECE.
Designation: Asst. Prof.
Unit title: Boolean Algebra and Logic Gates.
Objective: Introduction about Boolean theorems and properties, Logic Gates.
S.No. Subject Topics Periods Reference material
1 Basic Definitions, Axiomatic 2 2
definitions of Boolean Algebra.
2 Basic theorems and properties of 2 2
Boolean Algebra.
3 Boolean functions canonical and 3 1&2
standard forms, other logical operation,
2
4 Digital logic gates, integrated circuits. 2
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 3&5
2. Digital Design – Morris Mano, PHI, 3rd Edition. 1 to 4
Teaching aids: S.No.
1. O.H.P. 2
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 3/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : III Department: ECE.
Designation: Asst. Prof.
Unit title: GATE-LEVEL MINIMIZATION.
Objectives: To study about Map & Tabulation methods, Prime Implicants & Essential PI.
S.No. Subject Topics Periods Reference material
1 The map method, Four-variable map & 2 1
Five- variable map,
2 Product of sums simplification, Don’t 2 1
care conditions.
3 NAND and NOR implementation other 2 1&3
Two-level implementations.
Exclusive-Or function, Hardware 2 1
4
Description language (HDL).
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1 to 4
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 3
Teaching aids: S.No.
1. O.H.P. Nil
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 4/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : IV Department: ECE.
Designation: Asst. Prof.
Unit title: Combinational Logic.
Objective: The study of different Multivibrators.
S.No. Subject Topics Periods Reference material
1 Combinational Circuits, Analysis procedure. 1 1
2 Design procedure, Binary Adder-Subtractor. 2 1
3 Decimal Adder, Binary multiplier, magnitude 2 1
comparator.
4 Decoders, Encoders, Multiplexers. 2 2&3
5 HDL for Combinational circuits. 1 2&3
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1, 2 & 5
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 3&4
3. Modern Digital Logic Design- R.P. Jain.
3&4
Teaching aids S.No.
1. O.H.P. Nil
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 5/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : V Department: ECE.
Designation: Asst. Prof.
Unit title: SYNCHRONOUS SEQUENTIAL LOGIC.
Objective: Introduction about flip-flops.
S.No. Subject Topics Periods Reference material
1 Sequential circuits, latch. 2 1
2 Flip-Flops, Analysis of clocked 2 1&2
sequential circuits.
3 HDL for sequential circuits. 1 2
4 State Reduction and Assignment, 3 1&2
Design Procedure.
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1, 2 & 5
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 2&4
Teaching aids: S.No.
1. O.H.P. 5
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 6/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : VI Department: ECE.
Designation: Asst. Prof.
Unit title: Sequential Circuits-I.
Objective: To study Sequential circuits like flip-flops, Counters.
S.No. Subject Topics Periods Reference material
1 Registers & shift Registers. 3 1
2 Ripple counters synchronous counters, 3 1
other counters.
3 HDL for Registers and counters. 1 1&2
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1 to 4
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 4&5
Teaching aids: S.No.
1. O.H.P. 3
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 7/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : VII Department: ECE.
Designation: Asst. Prof.
Unit title: Sequential Circuits-II.
Objective: Mealy and Moore machines, Merger chart, Concept of minimal cover table.
S.No. Subject Topics Periods Reference material
1 Introduction, Random-Access 2 1
Memory, Memory Decoding.
2 Error Detection and correction Read 3 1&2
only memory.
3 Programmable logic Array. 1 2
4 Programmable Array logic. 1 2
5 Sequential Programmable Devices. 1
2
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1& 2
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition. 2 to 4
Teaching aids: S.No.
1. O.H.P. 6
2. Models. Nil
3. Simulation by Computer. Nil
PRRM ENGINEERING COLLEGE
SHABAD-509 217
Lesson Plan Subject code: 53024.
Class: II B.Tech Subject Title: Page number: 8/8.
Name of faculty:
Sem.: I-Sem Digital Logic Design V. Rajesh M.Tech.
Branch : CSE Unit Number : VIII Department: ECE.
Designation: Asst. Prof.
Unit title: ASYNCHRONOUS SEQUENTIAL LOGIC.
Objective: Introduction about .
S.No. Subject Topics Periods Reference material
1 Introduction, Analysis procedure, 2
1
Circuits with latches.
2 Design Procedure, Reduction of state 2 1&2
and Flow Tables.
3 Race-Free state Assignment Hazards, 3 1
4 Design Example. 1 1
Suggested references
Name of the book, authors, publishers, year of publication: S.No.
1. Digital Design – Morris Mano, PHI, 3rd Edition. 1 to 3
2. Switching & Finite Automata theory –Zvi Kohavi, TMH, 2nd edition 2
Teaching aids: S.No.
1. O.H.P. 2
2. Models. Nil
3. Simulation by Computer. Nil
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