Matching of Resistors and Capacitors

Group Leader Jepsy Asim Bob Sandra Shawn

Measuring Mismatch

w The mismatch between any two devices is expressed as a deviation of the measured device ratio from the intended device ratio. w The mismatch between one specific pair of devices can be calculated as: d = (x1/x2)-(X2/X1) = X1x2 - 1 (X2/X1) X2x1

Guidelines for Selecting Samples

w The sample should include twenty devices or more. w The sample should include devices drawn from three wafers or more. w The wafers should be selected from various positions in the wafer lot. w The sample devices should be selected from random locations on each wafer. w The sample should include wafers from more than one wafer lot, if possible. w Wafers that have been reworked should not be used for characterization. w The sample should be packaged using the same lead frames and encapsulation as production material.

Average Mismatch and Standard Deviation

w Based on computed mismatches, an average mismatch, md, can be derived as:
md = 1

N i=1

S di

w After the mean has been computed, the standard deviation of the mismatch can be calculated by: __
sd = ( 1

N-1 i = 1

S (di - md)2 ) 1/2

Systematic and Random Mismatch

w The mean, md, is a measure of the systematic mismatch between the matched devices. w The standard deviation, sd, is a measure of random mismatch caused by statistical fluctuations in processing conditions or material properties.

HISTOGRAM

Causes of Mismatch
w Random Statistical Fluctuations w Process Biases w Pattern Shifts w Diffusion Interactions w Stress Gradients and Package Shifts

Random Statistical Fluctuations

w Irregularities are found in every component
n

Polysilicon resistor

w All devices fall in one of these two categories:

n n

Peripheral fluctuations Areal fluctuations

Matched Capacitors
w Random mismatch due to peripheral and areal fluctuations has a standard deviation: Sc = (C)^ 1 --(ka + kp --- )^
(C)^

w Large Capacitors
n

Areal term dominates and the random mismatch becomes inversely proportional to the square root of capacitance.

Matched Capacitors

w Small Capacitors
n n

Dominates matching capacitors of different values. Example: 5pF matches a 50pF capacitor as well as it matches another 5pF capacitor.

Matched Resistors
w The random mismatch between a pair of matched resistors has a standard deviation of: 1 SR = (W)(R)^ --(ka + kp --- )^ W

Widths of Matched Resistors

w Extreme case where areal fluctuations dominate over peripheral fluctuations:
1 )^ W2 = W 1 ( R ---

R2

w Extreme case where peripheral fluctuations dominate over areal fluctuations:

1 )^1/3 --W2 = W 1 ( R

R2

WHAT IS PROCESS BIAS?

w The dimensions of geometries fabricated in silicon never exactly match those in the layout database because the geometries shrink or expand during photolithography, etching, diffusion and implantation. w The difference between the drawn width of a geometry and its actual measured width constitutes the term process bias.

PROCESS BIAS
w Next we study the implementation of such principles with passive devices (such as Resistors & Capacitors).

Resistors
w Polysilicon resistors using a silicide block exhibit high linearity,low capacitance to the substrate, and relatively small mismatches. w The linearity of these resistors in fact much depends on their length & width, necessitating accurate measurement and modeling for high precision applications.

Resistors
w Suppose 2 matched poly resistors having widths 2um and 4 um will have a process bias of 0.1um. This represents a systematic mismatch of no less than 2.4 %(0.512um). w If one matched resistors length is of 5um and other is 3um displays a typical mismatch on the order of 0.2%. w Approximately most processing biases should be of at least 0.1um. w But if the resistors of the above example were laid out in 20um segments then the ratio would be around 0.5um.

w For large values, resistors are usually decomposed into sorter units that are mapped out in parallel and connected in series.

w From the viewpoint of matching this layout is preferable, where the corners contribute significant resistance.

w When very accurate ratios are required (in integer values) this layout can be applied.

CAPACITORS
w They also experience systematic mismatches caused by process bias.(mostly by over etching).

w 2 poly poly capacitors, one 10x10um other 10x20um, after etching the bias is of 0.1um. The ratio of the 2 areas equal 0.5029 (almost equal to) mismatch of 0.6%.

CAPACITORS
w Ideally capacitor size often in analog circuits is given by

w Solution to the previous mismatch is to keep their parameter to area ratios same even if capacitors are of different sizes.

w Identically matched capacitors/unit sized are usually laid out as squares because this reduces their area to periphery ratio, which in turn minimizes the contribution of peripheral fluctuation to their random mismatch. w Larger capacitors/non unit sized are mapped out as rectangles.

w Theoretically these equations eliminate systematic mismatches due to process bias but not in practice.

CAPACITORS
w Process Bias experienced by rectangular capacitors are different from square ones. w Rectangular capacitors also increase contribution of peripheral fluctuation to random mismatches. w There are other effects like process bias leading to mismatches which are caused by boundary conditions of an object, stress, voltage modulation, dielectric polarization & pattern shifts.

What is a pattern shifts?

This is another error in matching mechanism due to surface discontinuities on substrates that are frequently displaced laterally during an epitaxial growth.

PATTERN SHIFTS
w Surface discontinuities left from the thermal annealing of the N-buried layer(NBL) propagate up through the monocrystalline silicone layer deposited during vapor-phase epitaxy. This discontinuous image is called an NBL shadow.

w Sometimes various edges of discontinuity shift by different amounts causing pattern distortion.

w Occasionally the surface discontinuities completely vanish during the course of epitaxy resulting in pattern washout.

Factors effecting shifts

w Magnitude of patterns depend on the mobility of absorbed reactants and crystal orientation. w Also high pressure, faster growth rate, presence of chlorine increase pattern shifts. w While high temperature tends to reduce pattern shifts.

PATTERN SHIFTS
w The NBL shadow is clear in the vicinity of minimum geometry NPN transistors. w It appears as a faint dark line. w Once the shadow is identified , the NBL shift can be estimated by dimensions of contact or narrow resistors. w Pattern shifts becomes potential concern whenever matched devices are laid out in a process that employs a patterned buried layer(such as NBL). w Not all components are reflected by pattern shifts like capacitors & poly resistors. But diffused resistors are usually enclosed in tanks or wells containing NBL.

PATTERN SHIFTS

Diffusion Interactions
w Dopants that form a diffusion do not all reside within the boundaries of its junction. w Metallurgical junction where acceptor concentration = donor concentration. w Tail portion of the junction that falls outside of the metallurgical junction.

Diffusion Interactions
w Tails of two adjacent diffusions will intersect with one another. w Different polarity n Counterdope n Higher sheet resistances n Narrower widths w Same polarity n Diffusions add n Reinforce each other n Lower sheet resistances n Greater widths

Diffusion Interactions
w To reduce mismatch, we add dummy resistors to either end of the array. w Must have exactly same width as the other resistors. w Should be connected to prevent the formation of floating diffusions.

Diffusion Interactions
w We can eliminate diffusion interactions without increasing the die area.

Stress Gradients and Package Shifts

w w w w Piezoresistivity Gradients and Centroids Common-Centroid Layout Location and Orientation

Stress Gradients and Package Shifts

w Different forms of packing affect the amount of stress. w Packaging for semiconductors
n

Metal
l

header

Plastic

Stress Gradients and Package Shifts

w Package shifts differences in measurements of electrical parameters before and after packaging. w Power packaging requires an intimate thermal union between the die and its leadframe or its header to minimize heat build up.

Stress Gradients and Package Shifts

w Low stress mold compounds do not reduce package stress significantly. w A better method involves coating each chip with polyimide resin prior to encapsulation. w Most products use plastic encapsulation with copper alloy headers or leadframes.

Piezoresistivity

Gradients and Centroids

w Isobaric contour plot

Gradients and Centroids

w Stress Gradient the rate of change of the stress intensity. w Smallest at the middle and slowly increases as it reaches the edges.

Gradients and Centroids

w Matched devices should be as close as possible to one another to reduce stress between them. w Assumption: stress gradient is constant in region. w Stress difference is proportional to the product of the stress gradient and the separation between them.

Gradients and Centroids

w ds = pccdccdelScc w pcc = piezoresistivity along a line connecting the centroids of the two matched device. w dcc = distance between the centroids w delScc = stress gradient

Common-Centroid Layout

Common-Centroid Layout
w 1. Coincidence w 2. Symmetry w 3. Dispersion w 4. Compactness

Location and Orientation

w Matched device should be where the stress gradients are the lowest. w Best location for matched devices are at the middle of the die. w Larger dice have more stress than smaller ones.

Location and Orientation

REFERENCES
w Razavi, Behzad. Design of Analog CMOS Integrated Circuits.New York: McGraw-Hill, 2001. w Johns, David and Ken Martin. Analog Integrated Circuit Design.Canada: John Wiley & Sons, Inc., 1997. w Hastings, Alan. The Art of Analog Layout. New Jersey: Prentice Hall, 2001.