DIGITAL CIRCUITS AND

SYSTEMS
Electronic & Communication Engineering
Danang University of Technology

Voltage Levels

Voltage
VDD
Logic value 1
V1,min
Undefined
V 0,max
Logic value 0
V SS (Gnd)

Logic values as voltage levels.

- Positive/Negative logic
system
-V0,max: max. voltage level that
a logic circuit recognizes as low
- V1,min: min. voltage level that a
logic circuit recognizes as high
- Exact V0,max ,V1,min values
depend on used technology,
normally 40% VDD and 60% VDD

x = "low"

x = "high"

(a) A simple switch controlled by the input x

Gate

Source

Drain
Substrate (Body)

(b) NMOS transistor

VG

VS

VD

(c) Simplified symbol for an NMOS transistor

NMOS transistor as a switch.

NMOS
- Most popular used transistor
is MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to Gnd for NMOS
- No physical difference
between source and drain
terminals
- By convention, the source
terminal is the node with lower
voltage for NMOS

Remarks
- Silicon is an electrical semiconductor.
- A transistor is fabricated by creating areas in the silicon
substrate that have an excess of either positive or negative
electrical charge.
- The gate terminal is made of poly-silicon which is
preferable to metal as it can be fabricated with extremely
small dimensions.
- The gate is electrically isolated from the rest of transistor by
a layer of SiO2.
- Transistors operation is governed by electrical fields caused
by voltages applied to its terminal

NMOS off
V

= 0V
SiO 2

= 0V
V

++++++ ++++
++++++
++++++
+++++++++
++++++
++++++
++++++
++++++
++++++
++++++
+++++++++++
+++++++++++
+++++++++ Substrate (type p) +++++++++

Source (type n)

Drain (type n)

(a) WhenV GS = 0 V, the transistor is off

NMOS transistor when turned off: back-to-back diodes represent

very high resistance (1012 ohm) between drain & source

VDD

NMOS on

VG = 5 V
SiO2

VS = 0 V

VD = 0 V
++++++ ++++
+++ ++++++
++++++
++++++
+++++++++++ +++++++++++++++++
+++++++++ ++ +++++++ ++++++++++

Channel (type n)
(b) When VGS = 5 V, the transistor is on

NMOS transistor when turned on: If the gate-to-source

voltage VGS is greater than a certain minimum positive voltage,
called VT (typically 0,2 VDD), then the switch is closed.

Channel
-The positive voltage on the gate attracts free electrons
existing in the type-n source and drain terminals & other
areas of the transistor towards the gate. Because of SiO2
layer, electrons gather in region of the substrate between
source & drain terminals, which results into channel
connecting source & drain.

+
W1

W2

L
L
(a) Small transistor

(b) Larger transistor

- The size of channel is determined by length L & width W

x = "high"

x = "low"

(a) A switch with the opposite behavior

Gate

Drain

Source

Substrate (Body)

VDD

(b) PMOS transistor

VG

VS

VD

(c) Simplified symbol for a PMOS transistor

PMOS transistor as a switch.

PMOS
- Most popular used transistor
is MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to to VDD for PMOS
- No physical difference
between source and drain
terminals
- By convention, the source
terminal is the node with higher
voltage for PMOS

VD

VD = 0 V

Operations

VD

- When the NMOS transistor is

turned on, its drain is pulled
down to Gnd

VG

VS = 0 V
Closed switch
whenVG = VDD

Open switch
whenVG = 0 V

(a) NMOS transistor

VS = VDD

VDD

VDD

VG

VD

VD
Open switch
whenVG = VDD

VD = VDD

- When the PMOS transistor is

turned on, its drain is pulled up
to to VDD

Closed switch
whenVG = 0 V

(b) PMOS transistor

NMOS and PMOS transistors in logic circuits.

VDD

5V

NMOS NOT

+
Vf

Vx

Vf

- VX=0V, tr is turned off -->

Vf=5V

Vx

(a) Circuit diagram

(b) Simplified circuit diagram

- When VX=5V, tr is turned

on, its drain is pulled down
to Gnd --> Vf=0V
- Exact Vf depends on R &
tr., typically is 0.2V

(c) Graphical symbols

A NOT gate built using NMOS

technology.

- R is used to limit the

current during turning on of
tr. (problem?)

VDD

NMOS NAND
- Series connection of NMOS to
create the logic AND function
- VX1= VX2=5V, tr is turned off -> Vf=5V
- When VX=5V, trs are turned
on, their drains are pulled down
to Gnd --> Vf will be closed to
0V

Vf
Vx

Vx

(a) Circuit

x1
x2

x1 x2

0
0
1
1

1
1
1
0

0
1
0
1

(b) Truth table

x1

- If only one of trs is turned off,

then Vf will be pulled up to 5V
- R is used to limit the current
(c) Graphical symbols
during turning on of tr.
NMOS realization of a NAND (problem?)
gate.
f

x2

V DD

NMOS NOR

x1 x2

Vf
Vx

Vx

0
0
1
1

x2

f
1
0
0
0

(b) Truth table

(a) Circuit

x1

0
1
0
1

- Parallel connection of
NMOS to create the logic
NOR function
- Either VX1= 5V or VX2=5V,
Vf will be closed to 0V
- If both Vx =0V --> Vf will
be pulled up to 5V

x1
x2

(c) Graphical symbols

NMOS realization of a NOR

gate.

VDD

VDD

NMOS AND
- AND realization by following a
NAND gate with an Inverter

Vf
A
Vx1

Vx2

x2

0
0
1
1

0
0
0
1

0
1
0
1

(b) Truth table

(a) Circuit

x1

x1 x2

x1
x2

(c) Graphical symbols

NMOS realization of an AND gate.

V DD

NMOS OR

VDD

Vf

Vx

Vx

(a) Circuit

x1
x2

x1 x2

0
0
1
1

0
1
1
1

0
1
0
1

- OR realization by
following a NOR gate with
an Inverter

(b) Truth table

x1
x2

(c) Graphical symbols

NMOS realization of an OR gate.

PDN Structure
VDD

- All mentioned structures can be

characterized by a block diagram
with PDN (pull-down network)
Vf
Vx
Vx

Pull-down network
(PDN)
n

Structure of an NMOS circuit.

PDN-PUN

- All mentioned structures can be

characterized by a block diagram
with PDN (pull-down network)
V DD
- The CMOS concept: replacing the
pull-up device with a pull-up network
(PUN) that is built using PMOS tr.
(PDN & PUN networks are
Pull-up network
(PUN)
complements of each other)
- For any given values of the inputs,
V f either the PDN pulls Vf down to Gnd
or the PUN pulls Vf up to VDD
Vx
- The PDN & PUN have equal
Pull-down network
(PDN)
numbers of trs. (the networks are
Vx
duals of one another)
- Whenever the PDN has NMOS trs.
Structure of a CMOS circuit. in series, the PUN has PMOS trs. in
parallel, and vice versa
1

CMOS NOT

VDD

R
Vf

VDD
Vx

T1
Vx

Vf NMOS realization of NOT gate

T2

(a) Circuit

T1 T2

0
1

on off
off on

1
0

- When Vx= 0V, T1 is ON &

T2 is OFF, Vf= 5V. Since T2
is OFF, no current flows
through trs.
- When Vx= 5V, T2 is ON &
T1 is OFF, Vf= 0V. Since T1
is OFF, no current flows
through trs.
- KEY: no current flows in
CMOS Inverter

(b) Truth table and transistor states

CMOS realization of a NOT gate.

Logic expression of NAND gate: f = x1 x2 = x1 + x2

Look at Truth Table, f=1 when either x1 or x2 = 0, thus PUN must
be active in this case (pull up Vf to 1), and two PMOS transistors
must be connected in parallel.
V DD
The PDN must implement the complement of f :
f = x1 x2
Since !f=1 when both x1 and x2 = 1, PDN must
T1
T 2 have two NMOS trs. connected in series.
Vf
Vx

Vx

T3

T4

(a) Circuit

x1 x2

T1 T2 T3 T4

0
1
0
1

on on off off
on off off on
off on on off

1
1
1
0

0
0
1
1

off off on on

(b) Truth table and transistor states

CMOS realization of a NAND gate.

CMOS NOR
VDD

f = x1 + x2 = x1 x2
Vx

T1

Vx

T2
Vf
T3

! f = x1 + x2

(a) Circuit

T4

x1 x2

T1 T2 T3 T4

0
1
0
1

on on off off
on off off on
off on on off

1
0
0
0

0
0
1
1

off off on on

(b) Truth table and transistor states

CMOS realization of a NOR gate.

CMOS AND
V DD

VDD

Vf
Vx

Vx

CMOS realization of an AND gate:

connecting a NAND gate to an Inverter

VDD

Example 3.1
Consider the following function:

f = x1 + x2 x3
Since all variables appear in their
complemented form, we can directly
derive the PUN: 1 PMOS tr. controlled by
x1 in parallel with a series combination of
2 PMOS trs. controlled by x2 & x3

For PDN, take complemented form of f

which leads to result as shown in Fig.

f = x1 + x2 x3 = x1 ( x2 + x3 )

Vf
Vx

Vx

Vx

Consider the following function :

Example 3.2

f = x1 + x2 + x3 x4
Build a circuit using CMOS to implement this functionality

VDD

Example 3.2
Consider the following function :

f = x1 + x2 + x3 x4
Vf
Vx

Vx

Step 1: Build PUN

f = x1 + x2 + x3 x4

Step 2: Build PDN

! f = x1 (x2 x3 + x4 )

Vx

Vx

Voltage Levels
V DD

Vf
Vx

Vx

Vx Vx
1

L L
L H
H L
H H

(a) Circuit

Vf
H
H
H
L

(b) Voltage levels

Voltage levels in the NAND gate

x1 x2

0
0
1
1

1
1
1
0

0
1
0
1

Voltage Levels
x1

x2

(a) Positive logic truth table and symbol of NAND gate

Positive logic system: higher voltages represent logic

value 1 & lower voltages represent logic value 0

Negative logic systems: the association between
voltages and logic values is reversed
x1 x2

1
1
0
0

0
0
0
1

1
0
1
0

x1
x2

(b) Negative logic truth table and symbol of NAND gate

Integrated Circuit Chips

Large variety of chips that implement various functions that are
useful in the design of digital hardware

The chips range from very simple ones with low functionality to
extremely complex chips

Eg. A digital hardware product may require a P to perform
some arithmetic operations, memory chips to provide storage
capability, and interface chips that allow easy connection to input
and output devices

Three main types of chips:

Standard chips

Programmable logic devices

Custom chips

Characterizing Standard Chips: Digital ICs

characterized several ways as follows:
Circuit Complexity
Gives measure of number of transistors or
gates
Within single package
Four general categories
SSI - Small Scale IC
< 12 gates or so
MSI - Medium Scale IC
< 100 gates or so
LSI - Large Scale IC
< 1000 gates or so
VLSI Very Large Scale IC
> 1000 gates or so

Circuit Topology
Describes the input and output structure of the device
Three general categories
TTL - Transistor Transistor Logic
Bipolar transistors on input and output
Output section looks like described circuit
Referred to as totem pole output
ECL - Emitter Coupled Logic
Bipolar
Logic done in emitter circuitry rather than
collector
High speed
MOS - Metal Oxide Semiconductors
MOS transistors on input and output

SSI Circuits
Lets look now at some SSI circuits
Referred to as glue logic in todays design
Most designs highly integrated
VLSI
Gate arrays
Array logics
Glue logic provides means of interconnection
SSI circuits fall into 3 general categories
Basic gates
Simple combinations of gates
Buffer and driver gates
Basic Gates
These implement fundamental logic functions
AND OR
NAND NOR
NOT

Standard Chip Examples

(a) Dual-inline package

VDD

Gnd

(b) Structure of 7404 chip

A 7400-series chip.

- 74LS00 is built by TTL tech.

- 74HC00 is fabricated by CMOS
technology
- Most popular chips used today
are the CMOS variants

DD

7404

7408

7432

x
x2
3
x
f

An implementation of f = x1 x2 + x2 x3

Pin 13

Pin 15

Pin 17

Pin 5

Pin 7

Pin 9

Pin 18
Pin 8

Pin 11

Pin 16
Pin 6

Pin 3

Pin 14
Pin 4

Pin 19

Pin 12
Pin 2

Pin 1

- Because of their low logic capacity, the standard

chips are seldom used in practice.
- One exception: many modern products include
standard chips containing buffers (logic gates that
are usually used to improve the circuit speed)

The 74244 buffer chip comprises 8 tri-state

buffers

Buffer

VDD

Vx

Vf

(a) Implementation of a buffer

f
(b) Graphical symbol

A non-inverting buffer

- When a logic gate has to drive a large

capacitive load, buffers are often used
to improve performance: f = x
- Buffers can be created with different
amounts of drive capability, depending
on the sizes of the transistors (will be
discussed later )
- As used for driving higher-thannormal capacitive loads, buffers have
trs. that are larger than normal
- Not only for high speed performance,
buffers are also used when high
current flow is needed to drive external
devices (e.g. use buffer to control LED)

Inverting Buffer
-Inverting buffer produces the same output as an inverter but
is built with relatively large transistors
- As shown in figure, for large values of n an inverting buffer
could be used for the inverter labeled as N1

N1
x

To inputs of
n other inverters
n

Inverter that drives n other inverters

e= 0
x

e
x

e= 1
x

(a) A tri-state buffer

Tri-state buffer has

additional control
input, called enable e

(b) Equivalent circuit

e

e x

0
0
1
1

Z
Z
0
1

0
1
0
1

(c) Truth table

Four types of tristate buffers.

(a)

(b)

x
(c)

x
(d)

Multiplexer
From Truth Table, derive canonical SOP form

f ( s, x1 , x2 ) = sx1 x2 + sx1 x2 + s x1 x2 + sx1 x2

) (

= sx1 x2 + x2 + s x1 + x1 x2 = sx1 + sx2

An application of tri-state buffers: Multiplexer

x1

s
x2

Multiplexer based on Logic gates

- A transmission gate: switch that connects x to f

- A switch is turned on by setting VS = 5V & V!S = 0V.
s

s
(a) Circuit

0
1

Z
x

(b) Truth table

s= 0
x

e
s

f=Z

s= 1
x

+ Vx= 0V: NMOS is

turned on, Vf = 0 (drain is
pulled down to Gnd
source)
+ Vx= 5V: PMOS is
turned on, Vf = 5V (drain
is pulled up to VDD
source)

f=x
(c) Equivalent circuit

f
s

(d) Graphical symbol

(e) Implementation

0
1

Z
x

Truth table: Transmission gate

e x

0
0
1
1

Z
Z
0
1

0
1
0
1

Truth table: Tri-state buffer

x1

s
x2

A 2-to-1 multiplexer built

using transmission gates.

A 2-to-1 multiplexer built

using tri-state buffers.

XOR Gate
x1

x1 x2

x2

0
0
1
1
f = x1 x2

f = x1 x2

0
1
0
1
Truth table

CMOS implementation

CMOS Exclusive-OR (XOR) gate.

0
1
1
0

x 1 x2
0
0
1
1

0
1
0
1

f = x 1 x2
0
1
1
0

(a) Truth table

x1

f = x1 x2

x2

(b) Graphical symbol

x1
x2
f = x1 x2

(c) Sum-of-products implementation

Logic gate based Exclusive-OR (XOR) gate.

PLD
x1 x2

x3

NOR plane
VDD

VDD

VDD

f1

f2

S1
VDD

S2
VDD

S3

NOR plane

An example of a NOR-NOR PLA.

Inputs

(logic variables)

Logic gates
and
programmable
switches

Outputs

(logic functions)

Programmable logic device as a black box.

x1 x2

xn

PLA
-Be realized in Sum-Of-Products form
- Each Pk is configured to implement
any AND function of xi
- Each fm is configured to implement
any OR function of Pk

Input buffers
and
inverters
x1 x1

xn xn
P1

OR plane

AND plane
Pk

f1

fm

General structure of a PLA (Programmable Logic Array).

x1

x2

x3

f1 = x1 x2 + x1 x3 + x1 x2 x3
Programmable
connections
OR plane
P1

P2

P3

P4

AND plane

Gate-level diagram of a PLA

How to implement ?

f1

f2

x1

x2

x3

OR plane
P1

P2

P3

P4

AND plane

- Customary schematic for the PLA in previous Figure

- Constraint: size of AND plane (only 4 product terms)

f1

f2

x1

x2

x3

PAL

P1
f1
P2

P3
f2
P4

AND plane

- Programmable switches present 2 difficulties in manufacturing

- PAL (Programmable Array Logic): programmable AND plane,
fixed OR plane -> less flexibility than PLA

Select

Enable
f1

Flip-flop
D

Clock

To AND plane

Extra circuitry added to OR-gate to provide additional functionality

 FF represent a memory element, depend on signal clock

that the OR gate output will be hold at certain time point
 Multiplexer selects output either from OR gate or from Q
output of the D-FF.

A SPLD programming unit (courtesy of Data IO Corp).

PAL-like
block

PAL-like
block

I/O block

I/O block

CPLD

PAL-like
block

PAL-like
block

I/O block

I/O block

Interconnection wires

Structure of a Complex Programmable Logic Device (CPLD).

CPLD Section
PAL-like block (details not shown)

PAL-like block

D Q

D Q

D Q

A section of the CPLD

- A CPLD consists of
many PAL-like blocks
interconnected via
switches
-A commercial CPLD has
2-100 PAL-like blocks
- Each PAL-l.b. has 3
macrocells.
- Each macrocell some
OR gates .

(a) CPLD in a Quad Flat Pack (QFP) package

To computer

Printed
circuit board

(b) JTAG programming

CPLD packaging and programming.

FPGA
-FPGA differ from CPLD (no
AND OR gates)
- Use logic blocks to
implement required functions
- 3 main resources: logic
blocks, I/O blocks,
interconnect. wires &
switches
- LB: 2-d array
- Interconnection: h. & v.
routing channels
A field-programmable gate array (FPGA).

LUT (Look-Up Table)

A two-input lookup table (LUT)

- Each L.B. typically has a small number of inputs & outputs.

- The most commonly used L.B. is LUT (lookup table) which
contains storage cells. The stored values (0/1) is produced as
the output of the storage cell.
- LUTs have various sizes which are defined by number of
inputs

Gate Multiplexer
From Truth Table, derive canonical SOP form

f ( s, x1 , x2 ) = sx1 x2 + sx1 x2 + s x1 x2 + sx1 x2

) (

= sx1 x2 + x2 + s x1 + x1 x2 = sx1 + sx2

LUT Multiplexer

x1
0/1
0/1

0/1
0/1
x2
(a) Circuit for a two-input LUT

x1 x2

f1

0
0
1
1

1
0
0
1

0
1
0
1

(b) f 1 = x 1 x 2 + x 1 x 2

x1
1
0

f1

0
1
x2
(c) Storage cell contents in the LUT

A two-input lookup table (LUT).

- A two-variable TT has 4 rows 

needs 4 cells.
- Three multiplexers controlled by
x1 & x2
- Explain principle ?

Example
x1
x2

Try to check its function by

using Truth Table

0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1

x3

A three-input LUT.

LUT Extra Circuit

Select

Out
Flip-flop

In1
In2

LUT

In3
Clock

Inclusion of a flip-flop in an FPGA logic block.

- The FF is used to store the value of its D input under control of
its clock input.

LUT in FPGA
- Two-input LUTs
- Four wires in each
routing channel
- Fig. shows
programmed states of
the L.Bs. & switches
+ Blue switches: ON
+ Black switches: OFF

x3

x1

x2

x1 0
0
0
x2
1

f1

x2 0
1
0
x3
0

f2

f1 0
1
1
f2
1

f1 = x1 x2
f 2 = x2 x3
f = f1 + f 2

Section of a programmed FPGA.

Remarks
- Each logic function must be small enough to fit within a single L.B.
- Users circuit is automatically translated into the required form by
using CAD tools
- When a circuit is implemented in an FPGA, the L.B. are
programmed to realize the necessary functions, and the routing
channels are programmed to make the required interconnections
between L.Bs.
- The storage cells in the LUTs in an FPGA are volatile: they lose their
stored values whenever the power supply for the chip is turned off.
- Instead of being re-programmed every time, a small memory chip
that holds its data permanently, called PROM, is included on the
circuit board that houses the FPGA. The storage contents are
automatically loaded from PROM to FPGA when power is applied to
the chips

Custom Chip
- Provide largest no. of logic gates, highest circuit speed, lowest power
- Whereas a PLD is prefabricated, a custom chip is created from scratch
- The process of defining where trs. & wires are placed on chip is called CHIP LAYOUT
- A typical chip has many long rows of logic gates with a large number of wires between rows
+ Blue wire on one layer/ Black wire on another layer
+ Blue square: hard-wired connection (via) between layers

x1

f2

x2
x3
f1

A section in a standard-cell chip. Chips made using this technology are

called ASICs (application-specific integrated circuits)

A sea-of-gates gate array

f1

x1

x2

x3

The logic function f1 = x2x3+x1x3 in the gate array