1

CHAPTER 2
COMBINATIONAL MOS LOGIC CIRCUITS

Introduction

In a combinational logic circuit, at any point of time, the output of the circuit depends on its
current input signals. They are also called as non-regenerative circuits. In seqsuential or
regenerative circuits, the output is not only a function of the current input signals, but also a
function of the previous values of the input signals. A sequential circuit includes a
combinational logic circuit and a register that holds the state. Figure 2.1 shows the block
diagram representation of a combinational and sequential circuit.

Figure 2.1 Combinational and Sequential Circuits

Static CMOS Design

Properties of static CMOS gates:-

1. One important property of a static CMOS gate is the output level and voltage swing.
The high and low output levels are always VDD and GND respectively. In other words,
the voltage swing is equal to the supply voltage. This results in high noise margins.
2. The logic levels are independent of the device size. Or, they are ratioless gates.
3. Very high input resistance and the steady-state input current is nearly zero.
4. Does not consume any static power as there is no direct path for current flow between
the supply and ground rails.
5. Always there is a path with finite resistance between output and VDD/GND

The static logic circuits discussed in this section are,

1. Static Complementary CMOS

2. Ratioed Logic
3. Pass-Transistor Logic

Static Complementary CMOS

 2

This is the most commonly used static logic gate. It is also called simply static CMOS. A static
CMOS gate is constructed by combining two networks, called the pull-up network (PUN) and
the pull-down network (PDN) as shown in Figure 2.2.

Figure 2.2 General Structure of Static CMOS Logic Gate

Function of PUN - to provide a connection between the output and VDD and generate logic 1
output

Function of PDN - to provide a connection between the output and VSS and generate logic 0
output

The PUN and PDN networks are constructed such that only one of the networks will be
conducting for a steady state input at any point of time. The PDNs are constructed using nMOS
transistors, while PUNs are made using pMOS transistors. nMOS transistor is closed when the
gate input voltage is high and is open for a low gate voltage. A PMOS transistor behaves just
the opposite; it is closed when the gate voltage is low and open when the gate voltage is high.

Realisation of CMOS Combinational Logic Circuits using PDN and PUN

In the combinational logic design, nMOS and pMOS transistors behave as switches. If two
nMOS transistors are connected in series, they act as switches in series. The combined switch
is closed only if both transistors are ON. This is equivalent to an AND function. Similarly,
NMOS transistors connected in parallel represent an OR function. Construction rules for
PMOS networks are just the opposite. A series connection of PMOS conducts if both inputs
are low, representing a NOR function, while PMOS transistors in parallel implement a NAND.
By using De Morgan’s theorems ( A + B = A.B and A.B. = A + B ), it can be shown that the
pull-up and pull-down networks of a CMOS structure are dual networks. This means that a
parallel connection of transistors in the pull-up network corresponds to a series connection of
the corresponding devices in the pull-down network.
 3

Figure 2.3 Series and parallel connections of nMOS and pMOS transisotrs

Therefore, to construct a CMOS gate, if PDN is implemented using series switches, the PUN
network will be implemented using parallel switches. The complete CMOS gate is constructed
by combining the PDN with the PUN. The number of transistors required to implement an N-
input CMOS logic gate is 2N.
The complementary gate is naturally inverting, implementing only functions such as
NAND, NOR, and XNOR. For constructing non-inverting gates such as AND/ OR/ XOR, an
extra inverter is added to the output stage.

Example 1: Construction of Two-input CMOS NAND gate

Logic Expression for a two-input NAND gate is F = A.B

General rule for construction:-

• Implement AND expressions using series connection of transistors.
• Implement OR expressions using parallel connection of transistors

Step 1: Construction of Pull-down network(PDN):

Use the un-inverted function below the bar to construct the pull-down network, which is an
AND function (A.B). Implement it using two nMOS transistors in series as shown below:-
 4

Step 2: Construction of Pull-up network(PUN):

Apply De Morgan’s law to the expression F = A.B = A + B
This is an OR expression. Use two pMOS transistors in parallel to implement this expression.
Mark the inputs with the same synbols A and B.

Step 3: Connect the upper end of the PUN to VDD and the lower end of the PDN to GND.
Connect the other two ends of both networks together to get the output point. The point where
PDN joins PUN is the output point. Figure 2.4 shows the complete circuit.

Truth Table

A B F

0 0 1
0 1 1
1 0 1
1 1 0

Figure 2.4 (a) 2-input CMOS NAND gate b) Truth Table

Verification of NAND Gate Truth Table:-

A=1, B=1
Both nMOS transistors in the PDN network are ON and the PUN network is OFF. The output
F is now pulled down to GND through the nMOS transistors to generate a ‘0’ output.
A=0, B=0
Both nMOS transistors are OFF. So, PDN is open . Both pMOS transistors are ON; so PUN is
closed. The output F is pulled up to VDD through the pMOS transistors to generate a ‘1’ output.
 5

A=0, B=1 or A=1, B=0

One of the nMOS transistors will be OFF. Due to the series connection of transistors in the
PDN, it is open. Since pMOS transistors are connected in parallel, a single closed pMOS
transistor is enough to connect the output point F to VDD. The output is therefore pulled up to
VDD through the closed pMOS transistor, generating a ‘1’ output.

Example 2: Implement the logic expression F = AB + CD using CMOS logic.

Solution:

Pull-down network construction:-

1. Observe the expression below the bar. There are two AND functions A.B and C.D. ,
and an OR function. Implement these AND functions using series combination of
nMOS transistors. A.B and C.D. Implement the OR function by parallel combination
of A.B and C.D to get the complete pull-down network.

Pull-up network:-

Apply De-Morgan’s law to the given expression

F = AB + CD = ( AB.CD) = ( A + B).(C + D)

( A + B) (C + D) (C + D) . (C + D)
OR-Parallel OR- Parallel AND-Series
 6

Combine the pull-up and pull-down networks to realise the final gate as shown in Figure 2.5.

Figure 2.5 CMOS Realisation of F = AB + CD

Example 3: Implement a CMOS logic gate for the expression F = D + A.( B + C )

Figure 2.6 Static CMOS logic gate for F = D + A.( B + C )

Exercise 1: Implement a 2-input CMOS NOR gate

Exercise 2: Implement a 2-input CMOS XOR gate

 7

PASS TRANSISTOR LOGIC

Basic Concept
In static CMOS circuits, input signals are always applied to the gate terminals and the
output is taken from the drain. Pass transistors follow a different approach. In pass transistor
circuits, inputs can be applied to source/drain terminals as well as gate. This feature reduces
the number of transistors required to implement a given logic, which is the major advantage of
a pass transistor based logic. For example, a two-input CMOS AND gate requires 6 transistors,
while pass transistor based AND gate needs only 2 transistors. Since pass transistor logic uses
less number of transistors, it has less physical capacitance than a CMOS circuit.
Pass transistor logic can be implemented using either nMOS or pMOS transistors. They
can be used to pass logic 1 or logic 0 voltage. However, they behave differently while passing
a 1 or 0 level signal.
An NMOS pass transistor acts as a perfect switch when passing a 0 but is poor at passing
a 1. Consider the nMOS pass transistor shown in Fig. 2.21. Input B is the control input. When
B=0, the pass transistor is OFF, with a high impedance output. When B=VDD, transistor turns
on. If A =0, the pass transistor passes the 0 logic level at the input A to the output point X to
generate ‘0’. If A= VDD, the output expected at ‘X’ is VDD. However, when the voltage at input
A reaches VDD − Vtn , nMOS pass transistor turns off. Hence the output only charges up to
VDD − Vtn . Therefore, we say that an nMOS pass transistor passes a strong 0 and a weak 1. For
a pMOS transistor, when the output node is pulled low, it drops to |Vtp|, and never reaches
0V. Therefore, pMOS pass transistor passes a strong 1 and a weak 0. Figure 2.21 shows the
nMOS pass transistor and truth table. Unlike CMOS logic, pass transistor truth table has three
output logic levels; 0,1 and Z.

(a)nMOS pass transistor

B A X
0 0 Z
0 1 Z
1 0 0
1 1 1

(b) Truth table

Figure 2.21 (a) nMOS pass transistor (b) Truth table
 8

Cascading of pass transistors

Since pass transistors cannot pass strong 1’s, they cannot be cascaded by connecting the output
of one transistor to the gate of another transistor. This is shown in Fig. When output of M1 is
connected to the gate of M2, point x can charge up to VDD − Vtn1 . If node C is at VDD, node Y
only charges upto VDD − Vtn1 − Vtn2 . On the other hand if output of M1 is connected to the source
of M2, there is only one threshold drop. Hence, proper way of cascading pass transistors
(Figure 2.22) is by connecting the output of the first transistor to the source of the second
transistor.

Figure 2.22 cascading of pass transistors (a) improper (b) proper

Example: Design of Pass transistor Based AND gate

Figure 2.23 shows the implementation of a two-input AND gate using nMOS pass transistors.

B A F
1 0 0
1 1 1
0 0 0
0 1 0

(a) (b) (c)

Fig 2.23 Pass-transistor based AND gate (a) Circuit (b)VTC (c)Truth table

Operation:
In this circuit, B is the control input. If B input is high, pass transistor M2 is ON. The
input A is copied to the output F. When B is low, M2 is OFF and the bottom pass transistor M1
is ON. Since the input to M2 is 0, it passes a 0 to the output. M1 is required to ensure that a 0
is passed to the output. Without M1, F will go to high impedance state for a low input on B.
Figure 2.23(b) shows the VTC of the pass transistor AND gate. Similar to CMOS gates,
the VTC of a pass transistor is data dependent. This can be verified as below: -
 9

Case 1: B=VDD
M2 is ON and M1 is OFF. The output follows the input till the input.

Case 2: A= VDD , B= 0 to VDD

Since the nMOS has a threshold of VDD/2, M2 is turned on until then and the output
remains close to zero. Once the bottom transistor turns off, output follows the input minus a
threshold drop.

Case 3: A=B= 0 to VDD

This is same as case 2.

Complementary Pass Transistor Logic (CPL)

Figure 2.24 Basic concept

Complementary Pass Transistor Logic (CPL) is a differential pass transistor logic

family used for high performance design. There are two networks, which accepts true and
complementary inputs and generate true and complementary outputs. Sample CPL gates are
shown in Figure 2.25.

(a) AND/NAND
 10

(b) XOR/XNOR

(c) OR/NOR

Figure 2.25 CPL Pass transistor networks

Properties of CPL gates:-

• Since the circuits are differential, complementary data inputs and outputs are always
available.
• Complex gates such as XORs and adders can be realized efficiently with less number
of transistors than CMOS.
• Since input signals are available in both polarities, no need to have extra inverters like
CMOS logic.
• Since the outputs are always connected to either VDD or GND, these gates are static.
Hence these circuits have noise resilience.
• The design is very modular. All gates use the same topology. Only the inputs are
permutated. This feature simplifies the design of gate libraries.
Disadvantages:
• Static power dissipation
• For a logic 1 input, the output of a pass transistor charges only upto VDD − Vt . This
voltage drop problem reduces noise margins and voltage swing.
 11

TRANSMISSION GATES

The transmission gate is a parallel combination of nMOS and pMOS transistors with gates
controlled by complementary voltages. This is the most widely used solution for the voltage
drop problem in pass transistors. It uses the complementary properties of pMOS and nMOS
transistors. Since nMOS passes a strong 0 it can be used to pull- down the output. Since pMOS
passes a strong 1, it is useful to pull-up the output. Thus by combining nMOS and pMOS in
parallel, we get perfect 1 and 0 at the output without any voltage drop. Figure 2.28 shows a
transmission gate and its symbol.

(a)Circuit (b)symbol representation

Figure 2.28 CMOS transmission gate

The transmission gate acts as a bidirectional switch controlled by the gate signal C.
When C=1, both pass transistors are on, allowing the signal to pass through the gate. In short,
A=B, if C=1. On the other hand, if C=0, both transistors are OFF, thus creating an open circuit
between nodes A and B (See Figure 2.29).

Working:

Figure 2.29 Operation of Transmission Gate

The behaviour of transmission gate in ON condition (C=1) for different inputs can be described
as below:-
A=1
Transmission gate is now enabled. The nMOS pass transistor pulls up the output node B
up to VDD-Vtn and turns off. However, since the pMOS transistor is also present, output
will charge all the way up to VDD through pMOS.
 12

A=0
Node B is initially at VDD. When A=0, the pMOS pass transistor by itself pulls down node B
to Vtp, and turns off. Since the parallel nMOS is also on, it pulls down node B all the way to
GND.
Thus it is possible to transmit strong 0’s and 1’s using the transmission gate. In other
words, transmission gate has rail-to-rail swing. In fact, transmission gate is called as a perfect
switch as it passes logic 1 and 0 without any degradation.
Transmission gates can be used to construct complex gates efficiently.

Example 1: 2- input MUX using transmission gates

Figure 2.30 Transmission gate based MUX

Figure 2.30 shows the implementation of a a 2-input MUX using transmission gate logic. The
logic expression for this circuit is given by,
F = ( A.S + B.S ) F = ( A.S + B.S ) (2.4)
Based on the value of the control signal S, the gate selects either A or b and passes to output.
A CMOS implementation of the same logic needs eight transistors instead of six.

Example 2: XOR gate

Figure 2.31 Transmission Gate XOR

Figure 2.31 shows a transmission gate based XOR.

 13

Working:
B=1
Transistors M1 and M2 act as an inverter and the transmission gate M3/M4 is off; hence
F = AB B = 0
M1 and M2 are disabled, and the transmission gate is ON. So, F = AB.

The combination of both results in the XOR function. Regardless of the values of A and B,
node F is always connected to either VDD or GND and is hence a low-impedance node. The
transmission gate implementation of XOR gate needs only 6 transistors, whereas CMOS logic
needs 12 transistors.

Other examples: Fast adder circuits and registers.

Performance of Pass -Transistor and Transmission Gate Logic:-

The pass-transistor and the transmission gate are not ideal switches because they have a series
resistance. This resistance can be calculated by finding the parallel resistance value of Rn and
Rp , which is generally constant for a particular transmission gate.,