Datasheet
DesignWare NVM IP Portfolio
Highlights
Overview
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Broadest portfolio of area-optimized
reprogrammable CMOS NVM IP
Synopsys DesignWare NVM IP provides reprogrammable Non-Volatile Memory (NVM)
supporting up to 512 kbits in standard CMOS and BCD process technologies with no
additional masks or processing steps. Small in area and low in power, DesignWare NVM
IP delivers industry-leading reliability in products that support write cycle endurance
from a few to one million.
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Few to 1,000,000 write cycle
endurance
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Standard CMOS and BCD processes
without additional masks or
processing steps
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15+ years of data retention at 150C
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Extended temperature range
including industrial and automotive
Grade 0 temperature ranges
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Integrated error checking and
correction (ECC) functionality
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Single core supply operation
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Silicon characterized and qualified
to exceed industry standards
Target Applications
Validated through rigorous characterization, qualification, and reliability testing, the
silicon-proven DesignWare NVM IP is delivered as a hard GDSII block and includes all
the required control and support circuitry including the charge pump and high voltage
distribution circuits. With more than 12 years of development history, the DesignWare
NVM IP is the area, power and reliability leader in reprogrammable CMOS NVM for
automotive, industrial and consumer products (Figure 1).
Bit count
512 kbit
1 kbit
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Mobile
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Automotive
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Internet of Things
Technology (optional)
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TSMC 250CMOS/BCD,
180CMOS/BCD, 152G, 130G,
90LP, 65LP, 55GP, 40LP
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GlobalFoundries 180IC
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SMIC 180G, 130G
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IBM 9SF and 9LP, 8RF, 7HV
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TowerJazz 180SL
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SilTerra 180G
Embedded flash
1 Mbit
Medium Density
OTP
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Support for 64 bit to 512 kbit
instances
AEON MTP EE
EEPROM
1 kbit
256 bit
AEON MTP
ULP
AEON FTP
TRIM
<256 bit
2 100
100 1k
1k 1M
Write cycle endurance
DesignWare NVM IP
Figure 1: DesignWare NVM IP block diagram
DIN[x:0]
ADDR[n:0]
CP_EN
DesignWare Medium Density
NVM IP
PROG
Key Features
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Support for 16 kbit to 512 kbit instances
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1,000 write cycle endurance
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10 year data retention at 125C
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Extended temperature range
(-40C to 125C)
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Integrated ECC functionality
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More than 5X the density of lower
bit-count NVM
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Less than 40 nanoseconds access time
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Convenient 32-bit word interface for
both program and read
DesignWare NVM IP Portfolio
READY
READ
NVM array
READ_BIAS_EN
ECC_DISABLE
Digital
controller
VDD_HV
ECC_USED
Sense amps
VDD
ECC_FAILURE
Scan Test
TM_DIGIN
TM_DIGOUT
TMR
TM[3:0]
TMS[5:0]
SCAN_IN
SCAN_TESTMODE
SCAN_OUT
VSS
PTF/FA Test Mode Access
Figure 2: DesignWare Medium Density NVM IP block diagram
DIN[31:0]
ADDR[n:0]
PROG
Charge
pump
Column logic
READ
NVM array
VDD (core)
DOUT[31:0]
Row logic
Synopsys DesignWare Medium Density
NVM IP delivers flash-like functionality
for up to 512 kbits of on-chip memory
in standard CMOS and BCD processes
without the requirement of extra masks or
processing steps. The NVM IP eliminates
the need for external EEPROM or flash
memory when integrating microcontrollers
in analog IC designs such as smart
sensors, power management and
touchscreen controller applications. The
NVM IP is delivered as a hard IP block
and includes all the necessary support
and control circuitry, including all highvoltage generation and distribution
required for programming (Figure 2).
ERASE_FAILURE
ERASE
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AEON MTP Ultra Low-Power (ULP)
ULP MTP targeted at RFID, NFC and
wireless applications
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AEON Few-Time Programmable
(FTP) Trim area-optimized NVM for
trimming applications
PROG_FAILURE
Charge
pump
SCAN_EN
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AEON Multiple-Time Programmable
(MTP) electrically erasable
programmable read only memory
(EEPROM) highest endurance and
reliability for data storage and EEPROM
replacement
Column logic
Row logic
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Medium Density up to 512 kbits
of on-chip memory with flash-like
functionality for analog integrated
circuits (ICs)
DOUT[x:0]
IP_EN
SCAN_CLK
Synopsys offers the broadest portfolio of
reprogrammable NVM in the world:
SCAN_RESET
DesignWare NVM IP Portfolio
READY
Digital
controller
VSS
Sense amps
Figure 3: DesignWare AEON MTP EEPROM NVM IP block diagram
DesignWare AEON MTP
EEPROM NVM IP
Key Features
Synopsys DesignWare AEON MTP
EEPROM NVM IP delivers EEPROM-level
performance in standard CMOS
processes. Supporting up to 8 kbits and
optimized for high write cycle endurance,
the EEPROM NVM IP block is available
in a wide range of process nodes from
250-nm to 40-nm. The IP supports up
to 1,000,000 write cycles and has been
qualified to automotive-level standards
in select process nodes. Delivered as a
hard IP block with all the necessary high
voltage and control circuitry included, the
AEON MTP EEPROM NVM IP is available
in advanced, high-voltage, and analog/
mixed signal nodes (Figure 3).
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Up to 100,000 (advanced processes)
and up to 1,000,000 (high voltage and
analog/mixed signal processes) write
cycle endurance
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Support for 128 bit to 8 kbit instances
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Up to 10 year data retention
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Industrial and automotive Grade 0
temperature ranges
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Available integrated ECC functionality
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Optimized for high endurance and
maximum reliability
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Single core supply operation
DesignWare AEON MTP ULP
NVM IP
DIN[15:0]
ADDR[n:0]
PROG
Developed in standard 180-nm/3.3V
process nodes, the MTP ULP NVM IP
offers best-in-class power consumption
and enables the MTP functionality
required by the Gen2 EPC and ISO15693
RFID standards. Delivered as a hard
IP block, the IP operates from a single
core supply and includes support and
control circuitry, including the high voltage
generation and distribution required for
programming (Figure 4).
VSS
Column logic
ERASE
READ
NVM array
Bias in
Osc in
DOUT
Row logic
Synopsys DesignWare AEON MTP ULP
NVM IP is optimized for power- and areasensitive wireless applications including
RFID and NFC tags used in everything
from logistics tracking to security
and authentication.
Charge
pump
READY
Digital
controller
VDD (core)
Sense amps
Figure 4: DesignWare AEON MTP ULP NVM IP block diagram
DIN[15:0]
ADDR[n:0]
PROG
Charge
pump
Column logic
READ
NVM array
Row logic
ERASE
DOUT
READY
Digital
controller
VDD (1.8V)
Key Features
VSS
Sense amps
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Support for 64 bit to 1 kbit instances
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Up to 100,000 write cycle endurance
Figure 5: DesignWare AEON FTP Trim NVM IP block diagram
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Peak programming current <10 A
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10-year data retention
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Read down to 0.9V
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16-bit word interface for erase,
program and read
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Single core supply operation
DesignWare AEON FTP Trim
NVM IP
High Reliability NVM IP
The reprogrammable DesignWare
AEON FTP Trim NVM IP is optimized
for area to replace fuses and one-time
programmable (OTP) technologies in
calibration and trimming applications
that require more than one programming
cycle. The IP requires no additional
masks or processing steps and offers a
similar footprint as OTP products with the
advantage of reprogrammability. Multiple
write cycles enable the end product to
be 100% electrically tested to improve
outgoing quality as well as enabling infield calibration updates to account for
environmental or device aging (Figure 5).
Synopsys is uniquely positioned in the NVM
IP space by having not only the technical
expertise in NVM design and test, but also
the facilities and capabilities to implement
the best-in-class processes andprocedures.
See one of the procedures in Figure 6 or
watch a video of the entire testing process.
Key Features
Deliverables
Figure 6: Characterization set of tests
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Support for 64 bit to 1 kbit instances
(analog/mixed signal processes)
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Databook
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128 bit to 2 kbit instances (high voltage
processes)
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Verilog behavior model
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Up to 10,000 write cycle endurance
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15+ years of data retention at 150C
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Industrial and automotive Grade 0
temperature ranges
About DesignWare IP
Synopsys is a leading provider of highquality, silicon-proven IP solutions for
SoC designs. The broad DesignWare
IP portfolio includes logic libraries,
embedded memories, embedded
test, analog IP, complete interface IP
solutions consisting of controller, PHY
and next-generation verification IP,
embedded processors and subsystems.
To accelerate prototyping, software
development and integration of IP into
SoCs, Synopsys IP Accelerated initiative
offers IP prototyping kits, IP software
development kits and IP subsystems.
Synopsys extensive investment in IP
quality, comprehensive technical support
and robust IP development methodology
enables designers to reduce integration
risk and accelerate time-to-market.
For more information on DesignWare
IP, visit http://www.synopsys.com/
designware.
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Production Test Flow document
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Abstract LEF and timing LIB files
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GDSII layout database
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Split Lot Characterization report
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Qualification report
Synopsys, Inc. 690 East Middlefield Road Mountain View, CA 94043 www.synopsys.com
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05/15.RP.CS5802.
