Lecture-54
Fully nested mode:
This mode is entered after initialized unless another is programmed
.the interrupt request are ordered in priority from 0 through I (0
highest). When an interrupt is acknowledged the highest priority
request is determined and its never placed on the bus. In addition to
this, the corresponding bit of is it. Their bit remains set until the
issues an end of interrupt (EOI) command immediately before
returning from the service routine, on if AEOI bit is set, until the
having edge of the last
. While the ISS bit is set, all further
interrupt of the same or lower priority are inhibited, while higher levels
will generate an interrupt (which will be acknowledge only if the
internel interrupt enable f/f has been re-enabled through software.
After the initialization sequence, IRO has the highest priority and IRY
the lowest priorities can be changed, in the rotating priority mode.
How the priority resolves the ISR set to allow service un interrupting
device .Will be clean by the following example.
Suppose IR2 and IR4 are unmasked and that an interrupt
signal comes in on the IR4 input .since IR4 is unmasked bit 4 of the
IRR will be sort. The priority resolves will detect that these bit is set
and seen. If any location needs to be taken. To do if checks the bits
in the in-service register (ISR) to see if a higher priority interrupt are
being serviced if a higher priority interrupt is being serviced if a higher
priority interrupt is being serviced. If a higher priority interrupt is being
serviced received as indicated by a being set for that input in the ISR,
then the priority resolves will take no action. If no higher priority
interrupt is being serviced. Then the priority resolve will activate the
circularly which send an interrupt signal to 8085 executes the IR4
interrupt service subroutine.
Now ,suppose that while the 8085 executing the TR4 arrives at
the IR2 input of the 8259 A since we assumed for this example that
IR2 was unmasked bit 2 if the IRR will be set .the priority resolve will
detect that this bit in the IRR is set and make a decision whether to
send interrupt to the processor. To make the decision ,the priority
resolves looks at the in-service register .If a higher priority bit is set
,then it means a higher priority interrupt is being service .the priority
resolves will wait until the higher priority bit in the ISR is reset before
be sending an interrupt signal to the
. For the new interrupt input .if
the priority resolves finds that the new interrupt has higher priority.
Than the highest priority then the highest priority interrupts being
serviced, it will set the appropriate bit in the ISR and then it sends.
A new INT signal to CPU in this example,IR2 has a higher
priority than IR4 so the priority resolves will set the bit 2 of the ISR
and send new INT signal. If 8085 interrupt function has been enabled
(EI) at the start if IR4 service sub routine, then this new INT will again
interrupt the CPU. Upon receiving
PIC sends the address if IR2
subroutine and CPU starts execution IR2 sub routine.
If the end of IR2 subroutine we send the PIC a command word
that resets the PIC a command word that resets bit 2 ISR so that
lower priority interrupts can be serviced A RESET instruction at the
end of the Ir4 subroutine return execution to the main program.
If IR4 procedure did not enable the interrupt input either EI
instruction the CPU would not expand to the IR2 caused INT signal
until it finished executing the IR4 dub-routine.
End of the interrupt (EOI):
The in service bit can reset automatically following the
trailing edge of the last in sequence
pulse (when AEOI bit in
ICWI is set) if AEOI=0, then ISR can be reset by a command word
that must be issued to the 8159A before returning from a service
routine (EOI command) an EOI command must be issued twice if in
the cascade mode, once for the master and for the corresponding
slave .there are two form if EOI command. Specified and nonspecified .when the 8259 A is operated in modes which procedure the
fully nested structure, it can determine which IS bit to reset on EOI.
When a non specific EOI commands is issued the 8259A will
automatically reset the highest IS bit of those that are set. Since in
the fully nested mode the highest IS level was necessary the last
level acknowledge & serviced .a non-specific EOI can be issued with
OCW2 (EOI=1, SL=0, R=0).
When a mode is used which may disturb the fully nested
structure, the 8259A may no longer may be able to determine the last
level acknowledged. In this case a specific and on interrupt must be
issued which includes as a part of the command the IS level to be
reset. A specific EOI can be issued with OCW2 ((EOI=1, SL=0, R=0)
L2-L0 IS the binary level of the IS bit to be reset.
It should be noted that an IS bit that is masked by an IMR bit
will not be cleaned by a non-specific EOI if the 8259A is the special
mask mode.
Automatic end of interrupt (AEOI) mode:
If AEOI=1in ICW4, then the 8259A will operate in AEOI mode
continuously until reprogrammed by ICW4,in this mode the 8259A will
automatically perform a non-specific EOI operation at the trailing
edge of the last interrupt acknowledge pulse(third pulse in
80/85,second in 86). Note that from a system start point. This mode
should be used only when a nested multilevel interrupt structure is
not required within a signal 8259A.
The AEOI mode can be used in a master 8259A and not a slave.
Automatic rotation: (equal priority devices)
If some application there are a number of interrupting device s
if equal priority .in this mode a device, after being serviced, receivers
the lowest priority, so advice requesting an interrupt will have to wait.
In the worst case until each other devices are serviced at most once.
For example if the priority and in service status is:
Before rotate (IR4 the highest priority requiring service);
IS states IS7
0
IS6.......................................IS0
1
Priority status
After
rotate
(IR4
was
serviced,
all
other
priorities
rotated
correspondingly)
IS states IS7
0
Priority status
IS6.......................................IS0
1
There are two ways to accomplish automatic rotation using OCW2,
the rotation or non-specific EOI command(R=1,SL=0,EOI=1) and the
rotate in automatic EOI mode which is set by (R=1,SL=0,EOI=1)and
cleared by (R=1,SL=0,EOI=1).
Specific rotation: (specific priority)
The programmer can change priorities by programming the
bottom priority and these fixing all other priority device, then IR6 will
have the highest one.
The set priority command is issued in OCW2 where R=1,
SL=0,L0-L2 is the
binary priority level code with bottom priority
device.
Observe that in this mode internal status is updated by software
control during OCW2.however it is independent if the end if interrupt
(EOI) command (also executed by OCW2). Priority changes can be
executed during an EOI command by using the rotate on specific EOI
command in OCW2 (R=1, SL=1, EOI=1) &L2- L0=IR level to receive
bottom priority.
Special mask mode:
Some application may require interrupt service routine to
dynamically after the system priority structure during its execution
under software content. For example, the routine may which to inhibit
lower priority requests for a portion of its execution but enable some
of them for another portion.
The difficulty here is that if an interrupt request is acknowledged
and an End of interrupt command did not resets its IS bit (i.e., while
executing a service routine) the 8259A would have inhibited. All lower
priority request with no easy way for the routine to enable them.
That is where the special mask mode comes in. In the special
mask mode, when a mask bit is set in OCW1, it inhibit further
interrupts at level and enables interrupts from all other levels(lower as
well as higher) that are not masked. Thus, any interrupts may be
relatively enabled by loading the mask register.
The special mask mode is set by OCW3 where ESMM=1,
SMM=1, and cleared where ESMM=1, SMM=0.
