Microprocessor and Microcontroller
7. This completes the 3-byte CALL instruction released by the 8259A.
In the AEOI mode the ISR bit is reset at the end of the third INTA
pulse.
8. Otherwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt sequence.
When the 8259A PIC receives an interrupt, INT becomes active and an
interrupt acknowledge cycle is started. If a higher priority interrupt occurs
between the two INTA pulses, the INT line goes inactive immediately after the
second INTA pulse. After an unspecified amount of time the INT line is activated
again to signify the higher priority interrupt waiting for service. This inactive
time is not specified and can vary between parts.
Programming the 8259A
The 8259A accepts two types of command words generated by the CPU:
Initialization Command Words (ICWs)
Before normal operation can begin, each 8259A in the system must be
brought to a starting pointed by a sequence of 2 to 4 bytes timed by WR pulses.
Operation Command Words (OCWs)
These are the command words which command the 8259A to operate in
various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A any time after initialization.
Initialization Command Words (ICWS)
Whenever a command is issued with A0 = 0 and D4 = 1, this is interpreted
as Initialization Command Word 1 (ICW1). ICW1 starts the initialization
sequence during which the following automatically occur.
a. The edge sense circuit is reset, which means that following
initialization, an interrupt request (IR) input must make a low-to-
high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
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