ISA: The Hardware Software Interface
Instruction Set Architecture (ISA) is where software meets
hardware
In embedded systems, this boundary is often flexible
Understanding of ISA design is therefore important
Instruction Set Definition
Operands: int32, uint32, int16, uint16, int8, uint8, float32, float64
Operations: four major types
Operator functions (add, shift, xor, mul, etc)
Memory access (load-word, store-byte, etc)
Control transfer (branch, jump, call, return, etc)
Privileged, and miscellaneous instructions (not generated by compiler)
Good understanding of compiler translation is essential
Inf3 Computer Architecture - 2011-2012
ISA Design Considerations
Simple target for compilers
Support for OS and HLL features
Support for important data types (floating-point, vectors)
Code size
Impact on execution efficiency (especially with pipelining)
Backwards compatibility with legacy processors
Provision for extensions
Inf3 Computer Architecture - 2011-2012
CISC vs RISC
CISC
Assembly programming HLL features as instruction
Small # registers, memory not that slow memory
operands
Code size must be small variable length
Backward compatibility complexity increases
RISC
Compilers Simple instructions
Large # registers, memory much slower than processor
load store architecture
Simple and fast decoding fixed length, fixed format
Inf3 Computer Architecture - 2011-2012
Operators and their Instructions
Integer Arithmetic
+
*
/
%
add
sub
mul
div
rem
Relational
<
<=
>
>=
==
!=
slt,
sle,
sgt,
sge,
seq
sne
sltu
sleu
sgtu
sgeu
C operator
Comparison
Reverse
Branch
==
seq
bnez
!=
seq
beqz
<
slt, sltu
bnez
>=
slt, sltu
beqz
>
slt, sltu
bnez
<=
slt, sltu
beqz
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Operators continued
Bit-wise logic
|
&
^
~
or
and
xor
not
Boolean
||
&&
(src1 != 0 or src2 != 0)
(src1 != 0 and src2 != 0)
Shifts
>>
>>
<<
(signed)
(unsigned)
shift-right-arithmetic
shift-right-logical
shift-left-logical
Inf3 Computer Architecture - 2011-2012
Operand Types
Usually based on scalar types in C
Type modifier
C type declarator
Machine type
unsigned
int, long
uint32
unsigned
short
uint16
unsigned
char
uint8
unsigned
long long
uint64
signed
int
int32
signed
short
int16
signed
char
int8
signed
long long
int64
boolean
uint1
float
float32
double
float64
&<type_specifier>
uint32
C defines integer promotion for expression evaluation
int16 + int32 will be performed at 32-bit precision
First operand must be sign-extended to 32 bits
Similarly, uint8 + int16 will be performed at 16-bit precision
First operand must be zero-extended to 16-bit precision
Inf3 Computer Architecture - 2011-2012
Instruction Operands - Registers
Registers
How many registers operands should be specified?
3:
R1 = R2 + R3
2:
R1 = R1 + R2
1:
+R1
32-bit RISC architectures normally specify 3 registers for dyadic
operations and 2 registers for monadic operations
Compact 16-bit embedded architectures normally specify respectively 2
and 1 register in these cases
Introduces extra register copying
E.g.
load
copy
add
sub
r1, [address]
r2, r1
r1, r3
r4, r2
# this is simply a re-use of r1, but the value of r1 had to be copied
into r2
Accumulator architectures now dead, but accumulators still widely used
in Digital Signal Processors (DSP).
E.g.
load [address1]
add 23
store [address2]
Inf3 Computer Architecture - 2011-2012
Instruction Operands - Literals
Constant operands
E.g. add r1, r2, 45
Jump or branch targets
Relative:
Normally used for if-then-else and loop constructs within a single function
Distances normally short can be specified as 16-bit signed & scaled offset
Permits position independent code (PIC)
Absolute
Normally used for function call and return
But not all function addresses are compile-time constants, so jump to contents of
register is also necessary
Load/Store addresses
Relative
Absolute
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How big do literals have to be?
Addresses
Always 32 (or 64 bits)
Arithmetic operands
Small numbers, representable in 5 10 bits are common
Literals are often used repeatedly at different locations
Place as read-only data in the code and access relative to program
counter register (e.g. MIPS16, ARM-thumb)
Branch offsets
10 bits catches most branch distances
32-bit RISC architectures provide 16-bit literals
16-bit instructions must cope with 5 10 bits
May extend literal using an instruction prefix
E.g. Thumb bx instruction
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Decision Making and Branches
Condition code based
sub $1, $2
Sets Z, N, C, V flags
Branch selects condition
ble : N or Z
(+) Sometimes condition set for free
(-) Extra state
Condition register based
slte $1, $2, $3
bnez $1 (or beqz $1)
(+) Simple and reduces number of opcodes
(-) uses up register
Compare and branch
combt lte $1, $2
(+) One instruction for a branch
(-) Too much work for an instruction
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Memory Access Operations
Memory operations are governed by:
Direction of movement (load or store)
Size of data objects (word, half-word, byte)
Extension semantics for load data (zero-ext, sign-ext)
Memory
access
load
word
lw
store
half-word
word
sw
signed unsigned
lh
byte
lhu
half-word
sh
byte
sb
signed unsigned
lb
lbu
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Addressing Mode Frequency
40
Addressing mode
Displacement
39
17
Immediate
Register
Scaled
55
32
TeX
16
0
1
spice
24
6
gcc
11
Indirect
43
10
20
30
40
50
60
Frequency of the addressing mode (%)
H&P
Fig. 2.7
Bottom-line: few addressing modes account for most of the
instructions in programs
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Displacement Addressing and Data Classification
Stack pointer and Frame pointer relative
5 to 10 bits of offset is sufficient in most cases
Register + offset
Generic form for accessing via pointers
Multi-dimensional arrays require address calculations
PC relative addresses
Useful for locating commonly-used constants in a pool of
constants located in the .text section
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Encoding the Instruction Set
How many bits per instruction?
Fixed-length 32-bit RISC encoding
Variable-length encoding (e.g. Intel x86)
Compact 16-bit RISC encodings
ARM Thumb
MIPS16
Formats define instruction groups with a common set of
operands
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MIPS 32-bit Instruction Formats
R-type (register to register)
three register operands
most arithmetic, logical and shift instructions
I-type (register with immediate)
instructions which use two registers and a constant
arithmetic/logical with immediate operand
load and store
branch instructions with relative branch distance
J-type (jump)
jump instructions with a 26 bit address
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MIPS R-type instruction format
6bits
5bits
5bits
5bits
5bits
6bits
opcode
regrs
regrt
regrd
shamt
funct
add
$1, $2, $3
special
$2
$3
sll
$4, $5, 16
special
$5
$4
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$1
add
16
sll
16
MIPS I-type instruction format
6bits
5bits
5bits
opcode
regrs
regrt
lw
$1, offset($2)
lw
$2
$1
beq
$4, $5, .L001
beq
$4
$5
(PC - .L001) >> 2
addi
$1, $2, -10
addi
$2
$1
0xfff6
16bits
immediatevalue/addr
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address offset
17
MIPS J-type instruction format
6bits
opcode
call func
26bits
address
call
absolute func address >> 2
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ISA Guidelines
Regularity: operations, data types, addressing modes, and
registers should be independent (orthogonal)
Primitives, not solutions: do not attempt to match HLL
constructs with special IS instructions
Simplify tradeoffs: make it easy for compiler to make choices
based on estimated performance
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