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Digital Lab Report 3 | PDF | Electronic Design | Digital Electronics
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Digital Lab Report 3

The document outlines experiments with various flip flops and counters. It includes circuit diagrams, truth tables, and objectives for experiments with RS flip flops using NAND and NOR gates, a JK flip flop examining set/reset and J/K inputs, a T flip flop, and asynchronous 3-bit up and down counters. Page numbers are provided for each experiment.

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علي علي
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312 views8 pages

Digital Lab Report 3

The document outlines experiments with various flip flops and counters. It includes circuit diagrams, truth tables, and objectives for experiments with RS flip flops using NAND and NOR gates, a JK flip flop examining set/reset and J/K inputs, a T flip flop, and asynchronous 3-bit up and down counters. Page numbers are provided for each experiment.

Uploaded by

علي علي
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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INDEX

Experiment No. Experiment Page Number

10.2.2 A RS flip-flop with NAND gate 3

10.2.2 B RS Flip-flop with NOR gate 4

10.4.2 Examining the Set and Reset 5


inputs of the JK Flip-fop

10.4.3 Examining the J and K inputs 5


of the JK flip-flop

10.4.4 Examine the JK Master-Slave 6


Flip-flop

10.5.2 Examining the T-flip-flop 7

11.2.2 Examining an Asynchronous 7


3-bit counter

11.2.3 Asynchronous 3-bit counter 8


with the measuring interface.

11.2.4 11.2.4 Asynchronous 3-bit 9


down counter with the
measuring interface

1
Flip Flops
10.2.2 A) RS flip-flop with NAND gate

Objective:

Set up an RS flip-flop from NAND gate as shown in the figure. Make the function table and compare
the function table with those of the NOR flip-flop

Circuit diagram:

Truth Table:

S R Q1 Q2
0 0 1 1
0 1 0 1
1 0 1 0
1 1 0/1 1/0

Simulation:

2
b) RS Flip-flop with NOR gate:

Circuit Diagram:

Truth Table:

S R Q1 Q2
1 0 0 1
0 1 1 0
0 0 1/0 0/1
1 1 0 0
Simulation:

3
10.4.2 Examining the Set and Reset inputs of the JK Flip-fop

Circuit Diagram:

A B Q1 Q2
0 0 1 1
0 1 0 1
1 0 1 0
1 1 1/0 0/1

10.4.3 Examining the J and K inputs of the JK flip-flop

Objective:

Examine the inputs J and K of the flip-flop. The set and reset remains unwired. Use the push button
as a clock generator.

Circuit Diagram:

4
Truth Table:

10.4.4 Examine the JK Master-Slave Flip-flop

Truth Table:

5
10.5.2 Examining the T-flip-flop

Objective: Set up a T flip-flop with a JK flip flop. Test the circuit with the measuring interface and
software.

Truth Table:

J K Q
1 1 0
1 1 1
1 1 0
1 1 1

11.2.2 Examining an Asynchronous 3-bit counter

Objective: set up an asynchronous 3 bit counter with T flip flops.

Circuit Diagram:

Truth Table:

Q1C Q1B Q1A


0 0 1
0 1 0
0 1 1
1 0 0
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0

6
11.2.3 Asynchronous 3-bit counter with the measuring interface.

Objective: Set up the Asynchronous 3-bit counter with the measuring interface and the software.

Truth Table:

Q1C Q1B Q1A


0 0 1
0 1 0
0 1 1
1 0 0
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0

7
11.2.4 Asynchronous 3-bit down counter with the measuring interface

Objective: Set up an Asynchronous 3-bit down counter with the measuring interface and the
software.

Truth Table:

Q1C Q1B Q1A


1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 1
0 0 0
1 1 1
1 1 0

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