KEMBAR78
Verilog Coding of MUX 8x1using If Else Statement | PDF | Teaching Methods & Materials
Scribd
Upload
535 views2 pages

Verilog Coding of MUX 8x1using If Else Statement

This document contains code for implementing an 8x1 multiplexer (MUX) in Verilog using two different methods: if-else statements and a case statement. The if-else implementation uses a series of if-else statements to assign the output z based on the value of the select lines sel. The case statement implementation uses a case statement to perform the same output selection based on sel. Both implementations define the inputs and output of the MUX module and use always blocks to specify the continuous assignment logic.

Uploaded by

Asif Muhammad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
535 views2 pages

Verilog Coding of MUX 8x1using If Else Statement

This document contains code for implementing an 8x1 multiplexer (MUX) in Verilog using two different methods: if-else statements and a case statement. The if-else implementation uses a series of if-else statements to assign the output z based on the value of the select lines sel. The case statement implementation uses a case statement to perform the same output selection based on sel. Both implementations define the inputs and output of the MUX module and use always blocks to specify the continuous assignment logic.

Uploaded by

Asif Muhammad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Verilog coding of MUX 8X1using if else statement

module mux(d, sel, z);

input [8:0] d;

input [2:0] sel;

output z;

reg z ;

always @( d or sel)

begin

if (sel==3'b000)

z= d[0];

else if(sel==3'b001)

z= d[1];

else if(sel==3'b010)

z= d[2];

else if(sel==3'b011)

z= d[3];

else if(sel==3'b100)

z= d[4];

else if(sel==3'b101)

z= d[5];

else if(sel==3'b110)

z= d[6];

else if(sel==3'b111)

z= d[7];

end

endmodule
verilog coding of 8x1 mux using case statement
module mux(d, sel, z);

input [8:0] d;

input [2:0] sel;

output z;

reg z ;

always @( d or sel)

begin

case(sel)

3'b000 : z=d[0];

3'b001 : z=d[1];

3'b010 : z=d[2];

3'b011 : z=d[3];

3'b100 : z=d[4];

3'b101 : z=d[5];

3'b110 : z=d[6];

3'b111 : z=d[7];

endcase

end

endmodule

You might also like