VLSI Design

(BEC-701)
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 Unit-3 Syllabus
Unit-3 Topics Slide Number
• Dynamic CMOS design: steady-state behavior 5-15
of dynamic gate circuits.
• Noise considerations in dynamic design 16-20

• Charge sharing, cascading dynamic gates 21-25

• Domino logic, np-CMOS logic 26-37
• Problems in single-phase clocking, two- phase 38-39
non-overlapping clocking scheme
• Sequential CMOS Logic Circuits 40-47
• Layout design
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 Dynamic vs. Static CMOS Design
• Static CMOS logic circuits consist of complementary PMOS pull up
network (PUN) and NMOS pull-down network (PDN) which work
concurrently.
• A typical static CMOS arrangement is shown below.

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 Dynamic vs. Static CMOS Design
• Dynamic logic on the other hand uses a sequence of pre-charge and
conditional evaluation phases.
• These phases are governed by the clock to realize complex logic functions.
• Two different forms of dynamic CMOS arrangement are shown below.

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 Dynamic CMOS Inverter
• The circuit diagram shows a dynamic CMOS
inverter.
• Clock is applied to the gate terminals of
PMOS and NMOS.
• Input is only applied to the gate terminal of
one of the NMOS.
• Timing Diagram------

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 Dynamic CMOS Design
• It is common practice to use the n-transistor version (shown below) of
dynamic CMOS design due to higher electron mobility.
• The clock signal (φ) decides the mode of operation in a dynamic CMOS
circuit.

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 Dynamic CMOS Design
• Precharge
When φ = 0, the output node “OUT” is precharged to VDD by the
PMOS transistor. During this time, the NMOS evaluation transistor
is OFF, so the NMOS logic network is isolated from ground by the
series network of NMOS transistors and hence no DC current flows
regardless of the values of the input signal. Input signals can change
with no effect to the output.

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 Dynamic CMOS Design
• Evaluation
When φ = 1, the precharge pull up transistor is OFF, and the
evaluation transistor is turned on. Depending on the values of the
inputs and the composition of the PDN, a conditional path between
OUT and (through the NMOS transistors) GND is created. If such a
path does not exist, the precharge value remains stored on the output
capacitor and a high output value is obtained during the evaluation
phase.

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 Dynamic CMOS Design
• The charging and discharging cycles of the output capacitor are shown
below.

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 Dynamic CMOS Design
• Features of Dynamic CMOS circuits
– Dynamic logic has higher speed than equivalent static family.
– It occupies less area as the number of transistors required is lower.
– The NMOS pull-down network implements the logic function.
– The noise margin does not depend on transistor ratios.
– It has lower power dissipation as it only consumes dynamic power.
– No static current path ever exists between VDD and GND.
– The load capacitance for the circuit is substantially lower which results in faster
switching speeds.
– Dynamic logic always require clock.
– It is impossible to operate the Dynamic logic at low speeds.
– Dynamic circuits are more sensitive to noise and timing errors.
– Dynamic logic is affected by charge sharing.
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 Steady-State Behaviour of Dynamic Logic
• The operation of all dynamic logic gates depends on temporary (transient)
storage of charge in parasitic node capacitances, instead of relying on
steady-state circuit behavior.
• This operational property necessitates periodic updating (refreshing) of
internal node voltage levels, since stored charge in a capacitor cannot be
retained indefinitely.

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 Steady-State Behaviour of Dynamic
Logic
• The pull-down network of a dynamic circuit starts to conduct when
the input signal exceeds the threshold voltage of the NMOS pull-
down transistor.
• If one waits long enough, the output eventually reaches GND. In the
high output state, the output impedance of the gate is very high,
since the output node is floating.
• Hence the output level is sensitive to noise and disturbances.

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 Noise Considerations in Dynamic Design
• The dynamic circuit concept results in simple and fast structure at the
expense of a reduced robustness with regards to noise. The logic has a
number of deficiencies that must be dealt with to guarantee functional
operation.
• Dynamic circuits suffer from issues like
1. Charge leakage,
2. Charge Sharing, and
3. Parasitic Capacitive Coupling.

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 Noise Considerations in Dynamic Design
• Charge Leakage
– The operation of the dynamic logic depends on the principles of dynamically storing a
charge on the output node (capacitor).
– Due to leakage currents, this charge gradually leaks away, resulting eventually in
malfunctioning of the gate. Charge leakage causes degradation in the logic high level.

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 Noise Considerations in Dynamic Design
• Charge Leakage
– Leakage during evaluation may be reduced by adding a pseudo-NMOS like pull-
up device known as bleeder transistor.

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 Noise Considerations in Dynamic Design
• Charge Sharing
– If during precharge all inputs are set at 0 and the capacitance
Ca is discharged. Assume further that input B remains at 0
during evaluation, while input A makes a 0 to 1 transition.
– Turning transistor Ma on, the charge stored originally on
capacitor CL is redistributed over CL and Ca.
– This causes a drop in the output voltage, which cannot be
recovered due to the dynamic nature of the circuit.
– Can be solved by pre-charging of internal nodes.

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 Noise Considerations in Dynamic Design
• Capacitive Coupling
– The high impedance of the output node makes the circuit very sensitive to
crosstalk effects.
– A wire routed over a dynamic node may couple capacitively and destroy the state
of the floating node.
– Another equally important form of capacitive coupling is the backgate (or output-
to-input) coupling

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 Noise Considerations in Dynamic Design
• Capacitive Coupling
– Any transition in Out2 can couple capacitively to Out1 via the parasitic capacitances of
M4.
– This can cause significant drop in the output of the dynamic gate which prevents the output
of the static NAND gate from going to 0.
– This can cause increased power dissipation and wrong evaluation.

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 Cascading Dynamic Gates
• Cascading of dynamic circuits is not as straightforward as connecting two
dynamic circuits in series.
• Simple series connection often results in poor signal integrity, reduced
noise margins and malfunctioning of the overall circuit.

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 Cascading Dynamic Gates
• Consider a cascaded connection of “2” dynamic CMOS inverters.
• During the precharge phase (i.e., CLK = 0), the outputs of both inverters are
precharged to VDD.
• If the primary input In makes a 0  1 transition, Out1 starts to discharge on
the rising clock edge. The second output should remain in the precharged state
of VDD as its expected value is 1.

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 Cascading Dynamic Gates
• When “Out1” exceeds the switching threshold of the second gate, a
conducting path exists between “Out2” and GND. “Out2” therefore
discharges as well, and wrongly so, as the correct output of the gate equals
1.
• This conducting path is only turned off when “Out1” reaches Vthn and shuts
off the NMOS pull-down transistor. This leaves “Out2” at an intermediate
voltage level. The charge loss leads to reduce noise margins and eventual
malfunction.

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 Cascading Dynamic Gates
• When “Out1” exceeds the switching threshold of the second gate, a
conducting path exists between “Out2” and GND. “Out2” therefore
discharges as well, and wrongly so, as the correct output of the gate equals
1.
• This conducting path is only turned off when “Out1” reaches Vthn and shuts
off the NMOS pull-down transistor. This leaves “Out2” at an intermediate
voltage level. The charge loss leads to reduce noise margins and eventual
malfunction.

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 Cascading Dynamic Gates
• The cascading problem arises because the outputs of each
gate—and hence the inputs to the next stages—are precharged
to 1.
• Setting all the inputs to 0 during precharge addresses this
concern.

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 Domino Logic
• Domino logic offers a simple technique to eliminate the need for
complex clocking scheme, by utilizing a single phase clock.
• A Domino logic module consists of a clocked n block(PDN)
followed by a static inverter.

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 Domino Logic
1. During precharge, the output of the n-type dynamic gate is charged
up to VDD, and the output of the inverter is set to 0.
2. During evaluation, the dynamic gate conditionally discharges, and
the output of the inverter makes a conditional transition from 0  1.

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 Domino Logic
• This ensures that all inputs to the next logic block are set to 0 after the
precharge periods. Hence, the only possible transition during the
evaluation period is a 0  1 transition.
• This transition can affect the next domino and so on like dominoes.

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 Domino Logic
• This ensures that all inputs to the next logic block are set to 0 after the
precharge periods. Hence, the only possible transition during the
evaluation period is a 0  1 transition.
• This transition can affect the next domino and so on like dominoes.

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 Features of Domino Logic
• Each gate requires N+4 transistors
• Logic evaluation propagates as falling dominoes hence minimum
evaluation period is determined by the logic depth.
• Domino gates can be made more immune to parasitic effects by
adding a level-restoring transistor to the static CMOS inverter.

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 Features of Domino Logic
• Using the inverter at the output:
– Results in a low-impedance output, which increases noise
immunity.
– Reduces the capacitance of the dynamic output node by
separating internal and load capacitances.
– Allows optimization of fan-out for high speed operation.
– The output of Domino logic family is non inverting (an issue).

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 Inverting Domino Logic
• A major limitation of domino logic is its inability to produce inverting logic
functions.
• A dual-rail domino also known as ‘Differential Cascade Voltage Switch”
(DCVS) solves this problem but increases power dissipation.

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 np-CMOS Logic
• The Domino logic requires an extra static inverter in the critical path to
make the circuit functional.
• np-CMOS, provides an alternate approach to cascading dynamic logic
by using two variants namely, n-block or n-tree and p-block or p-tree.

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 np-CMOS Logic
• General structure of np-CMOS logic(n-block or n-tree and p-block or p-
tree.

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 np-CMOS Logic
• In a p-tree logic gate, PMOS devices are used to build PUN, including
a PMOS evaluation transistor.
• The NMOS pre-discharge transistor drives the output low during
precharge. The output conditionally makes a 0  1 transition during
evaluation depending on its inputs.

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 np-CMOS Logic
• np-CMOS logic exploits the duality between n-tree and p-tree logic gates to
eliminate the cascading problem.
• If the n-tree is triggered by 𝐶𝐿𝐾 then the p-tree is triggered by 𝐶𝐿𝐾.
• During the precharge phase (CLK = 0), the output of the n-tree gate, Out1, is
charged to VDD, while the output of the p-tree gate, Out2, is pre-discharged to
0V.

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 np-CMOS Logic
• Since the n-tree gate connects PMOS pull-up devices, the PUN of the p-tree is
turned off at that time. During evaluation, the output of the n-tree gate can only
make a 1 0 transition, conditionally turning on some transistors in the p-tree.
• This ensures that no accidental discharge of Out2 can occur. Similarly, n-tree
blocks can follow p-tree gates without any problems, as the inputs to the n-gate
are pre-charged to 0.

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 Two-Phase Non-Overlapping Clocking
• Cascading in dynamic circuits may also be removed by using an isolated
technique to electronically separate the consecutive stages.
• NMOS switches or TG switches are employed to schedule the signal
connections between two adjacent stages.
• Each stage consists of a basic dynamic logic circuit and input switches.
• It is often called ϕi logic block, where i is an integer.
• If i = 2, it is known as two-phase non-overlapping clocking scheme.

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 Two-Phase Non-Overlapping Clocking
• The ϕ1 logic block consists of ϕ1-enabled TG switch and ϕ1-precharge
dynamic logic stage and the ϕ2 logic block consists of a ϕ2-enabled TG
switch and ϕ2-precharge dynamic logic stage.
For correct operation,
the two clock phases,
ϕ1(t) and ϕ2(t); must not
be overlapped.
Hence 𝜑1 . 𝜑2 = 0.

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 Sequential Logic Circuits
• In combinational circuits, outputs depend only on current inputs.
• A sequential circuit uses past data and hence requires storage of data
• To include the effect of previous inputs/outputs, memory elements are
required for storage.
• Most practical circuits are sequential in nature and use clock and memory.

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 S-R NOR Latch
• The storage (latching) mechanism of the cross-coupled bistable
inverter can be used to implement sequential circuits.
• The Set-Reset (S-R) latch can be implemented using a cross-coupled
NOR gate circuit.

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 CMOS Implementation of S-R NOR Latch

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 CMOS Implementation of S-R NAND Latch
• The S-R latch can be implemented using NAND gates as well.

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 Clocked & Level Sensitive S-R Latch
• For synchronous operation, a gated clock signal can be added.
• This circuit is NOR based level sensitive S-R Latch.

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 The J-K Flip Flop
• A major drawback of the S-R latch is that when S=R=1, both the outputs
RACE to become 0 which is not allowed.
• This issue is resolved by using the circuit below which is known as the J-K
(Jack Kilby) latch.

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 CMOS Implementation of J-K Latch

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 CMOS Implementation of D Latch

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 Topic----Layout
• Chips are specified with set of masks.

• Minimum dimensions of masks determine transistor size (and hence speed, cost, and
power)

• Feature size f = distance between source and drain set by minimum width of
polysilicon

• Feature size improves 30% every 3 years or so Normalize for feature size when
describing design rules

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 Design Rules

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 Layout-------Design Rules

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 Layout-----1. Lambda Based Design Rules

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 Design Rules for diffusion layer and Metal layer

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 Design Rules for transistors

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 Simplified Design Rules

• Conservative rules to get you started

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 CMOS Inverter
Layout
• Transistor dimensions specified as Width / Length
• Minimum size is 4 / 2, sometimes called 1 unit In f = 0.6 nm
process, this is 1.2 nm wide, 0.6 mm long

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 CMOS Inverter Layout
• Transistor dimensions specified as Width / Length
• Minimum size is 4 / 2, sometimes called 1 unit In f = 0.6 nm
process, this is 1.2 nm wide, 0.6 mm long.

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 References
1. Sung-Mo Kang & Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis &
Design”,Mcgraw Hill, 4th Edition.
2. Neil H.E.Weste, David Money Harris, “CMOS VLSI Design – A circuits and Systems
Perspective” Pearson, 4th Edition.
3. D. A. Pucknell and K. Eshraghian, “Basic VLSI Design: Systems and Circuits”, PHI, 3rd
Ed.,1994.
4. R. J. Baker, H. W. Li, and D. E. Boyce , " CMOS circuit design, layout, and simulation", Wiley
IEEE Press,2007.
5. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and Testable Design" ,
Jaico Publishing House.

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