6004 Spring 1998: L10

Clocking
and the
Dynamic Discipline

Recap: Latches and Flip-Flops

D Q is like a toll-gate
Level-sensitive: if G is high then
G value of D flows through to Q

D Q is like a air-lock
Edge-triggered: Q value updated
on rising transition of clock.
No direct path from D to Q

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 6004 Spring 1998: L10

Synchronous Sequential Circuit

Inputs Outputs
Acyclic
Combinational
Logic
Current Next
State State
Q1 D1

Q2 D2

Memory element:
CLK Latch or Flip-Flop
in every feedback loop

Issues: Specification, design, clocking and timing

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It is time to worry about timing...

• What memory element should we use in the

feedback loop?
– Edge-triggered flip-flop
– Level-sensitive latch
• Given the choice of memory element how fast
can we clock the logic circuit?
• What other timing constraints do we have to
obey?

• What about asynchronous inputs?

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 6004 Spring 1998: L10

Edge-Triggered Flip-Flop Timing

D must not change in this region

≥ ts Setup time = ts
≥ th Hold time = th

CLK

D
D Q

old Q
Q

tpd CLK-Q
tcd CLK-Q
5

Synchronous Circuit: Clocked Flip-Flop

1 2 7
I O CLK
CL
3 4
Q
Q D
5 6
CLK
D

t13 ≥ t35 ≥ t14 ≤ t46 ≤

Timing rules for flip-flop dictate:
t67 ≥ t15 ≥
6

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 6004 Spring 1998: L10

Flip-Flop Clocking Rules

1 2 7
CLK
3 4
Q

5 6

Clock period = t17

t17 = (t14 + t46 + t67) ≥ tpd C-Q + tpd C. L. + ts

Hold time constraint:

t15 = (t13 + t35) ≥ th tcd C-Q + tcd C.L. ≥ th
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Hold Time Constraint for Flip-Flop

tcd C-Q + tcd C.L. ≥ th

D Q D Q D Q

1-bit Counter Shift Register

We should design the flip-flop so

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 6004 Spring 1998: L10

Transparent D-Latch Timing

D Q Setup time = ts
≥ ts Hold time = th
Flow
through
G ≥ th

old Q
Q

D must not change in this region

9

Synchronous Circuit: Clocked Latch

1 2 7
I O CLK
CL
3 4
Q
Q D
5 6
CLK G
D

Will the clock shown above work?

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 6004 Spring 1998: L10

Avoiding Races: Latch Clocking Rules

1 2 7 8
CLK

3 4
Q
Need t25 > 0 to
9 5 6 avoid race
D condition

Timing rules for latch dictate:

t25 ≥ th t15 - t12 ≥ th

t12 ≤ t13 + t35 - th t12 ≤ tcd C-Q + tcd C.L. - th

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Clock Period Constraint for Latch

1 2 7 8
CLK
3 4
Q
ts
9 5 6
D
ts Assume
same as
Clock period = t28 = t96 tpd C-Q
t96 = (t94 + t46) ≥ tpd D-Q + tpd C.L.
assuming all other timing rules are satisfied!
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 6004 Spring 1998: L10

Clock Skew

D Q D Q
CL
CLKA
CLK
CLKB
wire delay w

CLKA

CLKB

Skew affects clock period and hold time constraints

13

Asynchronous Inputs = Trouble

Does this satisfy setup and hold time

constraints?

Input D Q D Q
CL
CLK

Need to sample asynchronous inputs reliably

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 6004 Spring 1998: L10

Coordinates

Office: NE43-258 Phone: x3-0454

email: devadas@mit.edu

Office hours: Tuesday 11AM-12PM, 3PM-4PM

Wednesday 2PM-4PM
Thursday 11AM-12PM, 3PM-4PM
or by appointment with Irena (x3-2322)

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