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D Latch - D Flip-Flop

This document discusses D latches and D flip-flops. It provides instructions on how to design a gated D-latch using NAND gates and inverters, including drawing a schematic and creating a truth table. It also compares the behavior of D latches and D flip-flops, noting that latches are level-sensitive and respond to input changes when the clock is high, while flip-flops respond only to input changes at the rising edge of the clock signal. A timing diagram is included to illustrate this difference.

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198 views4 pages

D Latch - D Flip-Flop

This document discusses D latches and D flip-flops. It provides instructions on how to design a gated D-latch using NAND gates and inverters, including drawing a schematic and creating a truth table. It also compares the behavior of D latches and D flip-flops, noting that latches are level-sensitive and respond to input changes when the clock is high, while flip-flops respond only to input changes at the rising edge of the clock signal. A timing diagram is included to illustrate this difference.

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Principles Of

Digital Design
Discussion: Flip-Flops

D-Latch Design
Latch vs. Flip-Flop Timing
D-latch Design
 Design a gated D-latch using NAND gates and inverters. Draw the
schematic and create a truth table for it. An implementation of simple
gates is provided for reference.
 Procedure D 2.0
Q
1. Convert NOR and AND to NAND
C
2.0 Q’
Logic schematic

2. Redraw schematic and create truth table

C D Q Q(next) D
2.0
Q
0 X 0 0
0 X 1 1 C
1 0 X 0
2.0 Q’
1 1 X 1
Truth table Logic schematic

Flip-Flops 2 DIGITAL DESIGN 101, University of California


Latch and Flip-Flop Comparison

 Compare the behavior of D latch and D flip-flop devices by completing


the timing diagram in the figure below. Assume each device initially
stores a 0.
Latches are level-sensitive since they respond to input changes
during clock width. (e.g. when clock is 1)
Flip-Flops respond to input changes only during the change in clock
signal, (e.g. at rising edge of clock signal)

Q(D latch)

Q(D flip-flop)

Flip-Flops 3 DIGITAL DESIGN 101, University of California


Latch and Flip-Flop Comparison
 Compare the behavior of D latch and D flip-flop devices by completing
the timing diagram in the figure below. Assume each device initially
stores a 0.
Latches are level-sensitive since they respond to input changes
during clock width. (e.g. when clock is 1)
Flip-Flops respond to input changes only during the change in clock
signal, (e.g. at rising edge of clock signal)

Q(D latch)

Q(D flip-flop)

Flip-Flops 4 DIGITAL DESIGN 101, University of California

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