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CHAPTER 2
AVR Architecture and Assembly
Language Programing
Department of Electrical Engineering
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Structure of Assembly Language
An Assembly language instruction consists of a
mnemonic, optionally followed by one or two
operands.
The operands are the data items being
manipulated.
The mnemonic s are the commands to the
CPU.
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General Purpose Registers (GPR)
Least Sigificant Bit (LSB)
Most Significant Bit (MSB)
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LDI Instruction
The LDI instruction copies 8-bit data into the
GPR. It has the following format:
LDI Rd,K
Note:
Load Rd (destination) with immediate value K, d
must between 16 and 31.
Example:
LDI R20, 0x25 ;load R20 with 0x25 (R20=0x25)
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ADD Instruction
It has the following format:
ADD Rd,Rr
Note:
ADD Rr to Rd and store the result in Rd.
Example:
LDI R16,0x25
LDI R17,0x34
ADD R16,R17
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The AVR Memory
1. Flash/Program/Code Memory
2. Data Memory
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The AVR Data Memory
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The AVR Data Memory
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Data Memory Size for AVR Chips
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LDS Instruction
(LoaD direct from data Space)
It has the following format:
LDS Rd,K
Note:
Load Rd (0≤n≤31) with the contents of the
location K, K is an address between $0000 to
$FFFF.
Example:
LDS R5,0x200 ;0x200 is address on SRAM
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LDS Instruction Example
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STS Instruction
(STore direct to data Space)
It has the following format:
STS K,Rr
Note:
Store register into location K, K is an address
between $0000 to $ FFFF.
Example:
STS 0x230,R25
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IN Instruction (IN from I/O)
IN Rd,A
Note:
Load an I/O location to the GPR (0≤n≤31),
(0≤A≤63).
Example:
IN R19,0x10
or
IN R19,PIND
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I/O Register
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OUT Instruction (OUT to I/O)
OUT A,Rr
Note:
Store register to I/O location.
Example:
IN R0,PIND
OUT PORTA,R0
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MOV Instruction
The MOV instruction is used to copy data among
the GPR registers of R0-R31.
MOV Rd,Rr ;Rd=Rr (copy Rr to Rd)
Example:
MOV R10,R20
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INC Instruction
INC Rd
Note:
Increment the contents of Rd by one (0≤n≤31).
Example:
INC R2 ;R2 = R2 + 1
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SUB Instruction
SUB Rd,Rr ;Rd = Rd – Rr
Example:
LDI R20,0x34
LDI R21,0x25
SUB R20,R21
STS 0x300,R20
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DEC Instruction
DEC Rd ; Rd = Rd -1
Example:
LDI R30,3 ;R30 = 3
DEC R30 ;R30 has 2
DEC R30 ;R30 has 1
DEC R30 ;R30 has 0
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COM Instruction
COM Rd
Note:
Inverts (complements) the content of Rd and
places the result back into the Rd register.
Example:
LDI R16,0x55
COM R16 ;R16 = 0xAA
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AVR Status Register
C, the carry flag: this flag is set whenever
there is a carry out from D7 bit.
Z, the zero flag: the zero flag reflects the result
of an aritmethic or logic operation.
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AVR Status Register
N, the negative flag: binary representation of
signed numbers uses D7 as the sign bit.
V, the two’s complement overflow flag: this
flag supports two’s complement aritmethics.
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AVR Status Register
S, the sign bit: this flag is the result of
Exclusive-ORing of N and V flags.
H, the half carry flag: if there is a carry from
D3 to D7 during ADD and SUB operation.
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Flags Example
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Flags Example
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Flags Example
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AVR Data Type
Hex numbers; put 0x or 0X or $ in front of the
number like this: 0x98, 0X76, $99.
Binary numbers; 0b or 0B in front of the
number like this: 0b1010, 0X01110000.
Decimal numbers; simply use the decimal.
ASCII characters; use single quotes as
following: LDI R16,’2’.
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Assembler Directives
.EQU(equate)
This used to define a constant value or fixed
address.
Example:
.EQU COUNT = 0x25
..........................
LDI R21,COUNT ;R21 = 0x25
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Assembler Directives
.INCLUDE
The .include directive tells the AVR assembler to
add the contents of a file to our program.
Example:
.INCLUDE “M32DEF.INC”
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Program Counter in the AVR
Each Flash memory location in 2 bytes wide.
In ATMega32, whose Flash is 32Kbytes, the
Flash is organized as 16K x 2, and its program
counter is 14 bits wide (214 = 16K memory
location).
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ROM Memory in the AVR
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Program ROM Width for the AVR
Add Bus
Data Bus
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The AVR Wakes Up
At what address does the CPU wake up when
power is applied? Each microprocessor is
different.
The AVR microcontroller wakes up at memory
address $0000 when it is powered up, then PC
(Program Counter) has the value of 0000 in it.
The first opcode must be burned into memory
location $0000 of program ROM by using the
.ORG statement in the source program.
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.ORG (origin) Directive
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The Machine Code
Instruction “LDI Rd,K” in Binary:
Instruction “LDI Rd,K” in Hex:
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The Machine Code
Instruction “ADD Rd,Rr” in Binary:
Instruction “ADD Rd,Rr” in Hex:
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The Machine Code
IN Instruction:
OUT Instruction:
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The Machine Code
STS Instruction:
LDS Instruction:
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The Machine Code
JMP Instruction:
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Harvard Architecture in the AVR
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Futures of RISC
Future 1:
RISC processors have a fixed instruction size
(2-byte instructions with very few 4-byte).
In a CISC microcontroller such as the 8051,
instructions cab be 1, 2, or even 3 bytes.
This is like bricklayer working with bricks of
the same size as opposed to using bricks of
variable sizes. Of course, it is much more
efficient tu use bricks of the same sizes.
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Futures of RISC
Future 2:
RISC architecture is a large number of
registers, all RISC architecture have at least 32
register.
One advantage is that it avoids the need for
large stack to store parameters.
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Futures of RISC
Future 3:
RISC processors have a small instruction set,
hardwiring of RISC instruction take no more
than 10% of transistors (CISC 40-60%).
Future 4:
More than 95% of instructions are executed
with only one clock cycle.
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Futures of RISC
Future 5:
In CISC processor, there is one set of buses for
the address and another set of buses for data.
In RISC processor, there are four sets of buses:
(1) a set of data buses for carrying data in and
out of the CPU, (2) a set of address buses for
accessing data, (3) a set of buses to carry the
opcodes, (4) a set of address buses to access
the opcodes.
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Futures of RISC
Future 6:
RISC “load-store architecture”
– Only load/store access memory
– Benefit: simpler hardware easier to pipeline,
higher performace
CISC “register-memory architecture”
– All operations can have an operand in memory
– Benefit: fewer instructions smaller code
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References
Mazidi, M.A., NAIMI, S., NAIMI., S. (2011). The
AVR Microcontroller and Embedded System.
New York: Prentice-Hall.
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Thank You
Khusnulhidayat[at]yahoo.com
Electrical Engineering Department
University of Muhammadiyah Malang (UMM)
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