PULSE AND DIGITAL CIRCUITS

What is a Counter?
A counter is a device which can count any particular event on the basis of how
many times the particular event(s) is occurred. In a digital logic system or computers,
this counter can count and store the number of time any particular event or process
have occurred, depending on a clock signal. Most common type of counter is sequential
digital logic circuit with a single clock input and multiple outputs. The outputs represent
binary or binary coded decimal numbers. Each clock pulse either increase the number
or decrease the number.

Synchronous Counter
Synchronous generally refers to something which is coordinated with others
based on time. Synchronous signals occur at same clock rate and all the clocks follow
the same reference clock.In previous tutorial of Asynchronous Counter, we have seen
that the output of that counter is directly connected to the input of next subsequent
counter and making a chain system, and due to this chain system propagation delay
appears during counting stage and create counting delays. In synchronous counter,
the clock input across all the flip-flops use the same source and create the same clock
signal at the same time. So, a counter which is using the same clock signal from the
same source at the same time is called Synchronous counter.

4 Bit Synchronous Counter.

We can see that the external clock pulses (pulses to be counted) are fed directly to
each of the J-K Flip-Flop in the counter chain and that both the J and K inputs are all
tied together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states in response to the
common clock signal, advancing one state for each pulse.
The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-
flop FFA, but the J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the input and output of
the previous stage. These additional AND gates generate the required logic for the JK
inputs of the next stage.If we enable each JK flip-flop to toggle based on whether or not
all preceding flip-flop outputs (Q) are “HIGH” we can obtain the same counting
sequence as with the asynchronous circuit but without the ripple effect, since each flip-
flop in this circuit will be clocked at exactly the same time.Then as there is no inherent
propagation delay in synchronous counters, because all the counter stages are
triggered in parallel at the same time, the maximum operating frequency of this type of
frequency counter is much higher than that for a similar asynchronous counter circuit.

AsynchronousCounter
An asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
Asynchronous counters are also called ripple-counters because of the way the clock
pulse ripples it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2 n if n flip-flops are
used. For a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may
count up or count down or count up and down depending on the input control. The
count sequence usually repeats itself. When counting up, the count sequence goes
from 0000, 0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc. When counting down the
count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001, 0000, 1111,
1110, ... etc.
The complement of the count sequence counts in reverse direction. If the
uncomplemented output counts up, the complemented output counts down. If the
uncomplemented output counts down, the complemented output counts up.
There are many ways to implement the ripple counter depending on the
characteristics of the flip flops used and the requirements of the count sequence.

 Clock Trigger: Positive edged or Negative edged

 JK or D flip-flops
 Count Direction: Up, Down, or Up/Down
Asynchronous counters are slower than synchronous counters because of the delay in
the transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all
the bits in the count change synchronously with the assertion of the clock. Examples of
synchronous counters are the Ring and Johnson counter.

4 Bit Asynchronous Counter

A 4 bit asynchronous UP counter with D flip flop is shown in above diagram. It is

capable of counting numbers from 0 to 15. The clock inputs of all flip flops are cascaded
and the D input (DATA input) of each flip flop is connected to a state output of the flip
flop.
That means the flip flops will toggle at each active edge or positive edge of the
clock signal. The clock input is connected to first flip flop. The other flip flops in counter
receive the clock signal input from Q’ output of previous flip flop. The output of the first
flip flop will change, when the positive edge on clock signal occurs.
In the asynchronous 4- bit up counter, the flip flops are connected in toggle mode, so
when the when the clock input is connected to first flip flop FF0, then its output after one
clock pulse will become 20.

The rising edge of the Q output of each flip flop triggers the clock input of its next
flip flop. It triggers the next clock frequency to half of its applied input.
In the asynchronous 4- bit up counter, the flip flops are connected in toggle mode, so
when the when the clock input is connected to first flip flop FF0, then its output after one
clock pulse will become 20.

The rising edge of the Q output of each flip flop triggers the clock input of its next
flip flop. It triggers the next clock frequency to half of its applied input. The Q outputs of
every individual flip flop (Q0, Q1, Q2, Q3) represents the count of the 4 bit UP counter
such as 20 (1) to 23 (8).

Working of asynchronous up counter is explained below,

Let us assume that the 4 Q outputs of the flip flops are initially 0000. When the
rising edge of the clock pulse is applied to the FF0, then the output Q0 will change to
logic 1 and the next clock pulse will change the Q0 output to logic 0. This means the
output state of the clock pulse toggles (changes from 0 to1) for one cycle.
As the Q’ of FF0 is connected to the clock input of FF1, then the clock input of second
flip flop will become 1. This makes the output of FF1 to be high (i.e. Q1 = 1), which
indicates the value 20. In this way the next clock pulse will make the Q0 to become high
again.
data structure and programming
#include <stdio.h>
#define MAX 100
int main()
{
int arr[MAX],limit;
int i,j,temp;

printf("Enter total number of elements: ");

scanf("%d",&limit);
/Read array/
printf("Enter array elements: \n");
for(i=0; i<limit; i++)
{
printf("Enter element %3d: ",i+1);
scanf("%d",&arr[i]);
}
/sort elements in Ascending Order/
for(i=0; i<(limit-1); i++)

for(j=0; j<(limit-i-1); j++)

{
if(arr[j]>arr[j+1])
{
temp=arr[j];
arr[j]=arr[j+1];
arr[j+1]=temp;
}
}
}
printf("Array elements in Ascending Order:\n");
for(i=0; i<limit; i++)
printf("%d ",arr[i]);

printf("\n");

/sort elements in Descending Order/

for(i=0; i<(limit-1); i++)
{
for(j=0; j<(limit-i-1); j++)
{
if(arr[j]<arr[j+1])
{
temp=arr[j];
arr[j]=arr[j+1];
arr[j+1]=temp;
}
}
}

printf("Array elements in Descending Order:\n");

for(i=0; i<limit; i++)
printf("%d ",arr[i]);

printf("\n");

return 0;
}
PROGRAMMING
Emplement an array it’s initialition and content display.
#include<stdio.h>
#include<stdio.h>
void main()
{
inta[5],i;
clrscr();
printf(“\nEnter the elements in array:”);
for(i=0;i<5;i++)
{
scanf(“%d”,a[i]);
}
printf(“\nElements of array are:”);
for(i=0;i<5;i++)
{
printf(“\n%d”,a[i]);
}
printf(“\nsize of given array= %d bytes”,sizeof(a));
getch();
}

OUTPUT
Enter the elements in array:1
2
3
4
5
Elements of array are:
1
2
3
4
5
Size of array = 10 bytes
PROGRAMMING
To write a C program to print the day for an input of date, month and year.

#include <stdio.h>
#include <conio.h>
void main()
{
int month[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
char week[7][10] ;
int date, mon, year, i, r, s = 0 ;
clrscr();
strcpy(week[0], "Sunday") ;
strcpy(week[1], "Monday") ;
strcpy(week[2], "Tuesday") ;
strcpy(week[3], "Wednesday") ;
strcpy(week[4], "Thursday") ;
strcpy(week[5], "Friday") ;
strcpy(week[6], "Saturday") ;
printf("Enter a valid date (dd/mm/yyyy) : ") ;
scanf("%d / %d / %d", &date, &mon, &year) ;
if( (year % 400 == 0) || ((year % 4 == 0) && (year % 100 != 0)) )
{
month[1] = 29;
for(i = 0 ; i< mon - 1 ; i++)
{
s = s + month[i] ;
s = s + (date + year + (year / 4) - 2) ;
s=s%7;
}
printf("\nThe day is : %s", week[s]) ;
}
getch() ;
}
OUTPUT:-
Enter a valid date (dd/mm/yyyy) : 02/11/1977

The day is : Wednesday