AMERICAN
INTERNATIONAL
UNIVERSITY-
BANGLADESH
Faculty of Engineering
LAB Title: Implementation of Asynchronous and synchronous counters using
flip-flops.
LAB No: 07 Date of Submission: 08-09-2024
Course Title: DIGITAL LOGIC AND CIRCUITS LAB
Course Code: EEE3102 Section: C
Semester: Summer 2023-24 Course Teacher: MD. Ali Noor
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Group Name/No.: 06
N Name I Program Signature
o D
1 Asef Abdullah 22-49923- BSc [CSE]
3
2 Md. Afiqul Islam 22-47874- BSc [CSE]
2
3 FARZANA ZAMAN 22-48258- BSc [CSE]
2
4 Sufian, Md. Waliullah 22-49964- BSc [CSE]
3
5 Ahsan, Md. Ridwan Bin 22-49953- BSc [CSE]
3
Faculty use only
FACULTYCOMMENTS
Marks
Obtained
Total Marks
Title: Implementation of Asynchronous and synchronous counters using flip-flops.
Introduction:
Counters are combinations of flip-flops arranged so that they can remember how many clock pulses have
been applied over some specified interval. The flip-flops are often interconnected so that only a portion of
their available binary states can be supported. If there are N flip-flops being used in a counter, the number of
be a modulo K (or MOD K) counter. Some applications will require a separate output to indicate each of the
states, alternatively, other applications may require only one output pulse every Kth state.
Counters are classified into two broad categories according to the way they are clocked: asynchronous and
synchronous. In asynchronous counters, commonly called ripple counters, the first flip-flop is clocked by the
external clock pulse and then each successive flip flop is clocked by the output of the preceding flip-flop. In
synchronous counters, the clock input is connected to all of the flip-flops so that they are clocked
simultaneously.
The objective of this experiment is designing of the following counters using J-K Flip-Flops (IC 74LS76)
(a) n-bit Binary Asynchronous Counter
(b) n-bit Binary Synchronous Counter
Theory and Methodology:
Asynchronous counter
A three-bit asynchronous counter is shown in the figure 1. The external clock is connected to the clock input
of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of the Q output of FF0. Because of the inherent propagation delay
through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF0 can never
occur at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an
asynchronous operation.
Figure 9.1 gives a three-bit counter capable of counting from 0 to 7. The clock inputs of the three flip-flops
are connected in cascade. The T input of each flip-flop is connected to a constant 1, which means that the
state of the flip-flop will be reversed (toggled) at each positive edge of its clock. We are assuming that the
purpose of this circuit is to count the number of pulses that occur on the primary input called Clock. Thus the
clock input of the first flip-flop is connected to the Clock line. The other two flip-flops have their clock inputs
driven by the Q output of the preceding flip-flop. Therefore, they toggle their state whenever the preceding
flip-flop changes its state from Q = 1toQ = 0, which results in a positive edge of the Q signal.
Figure 9.1 shows a timing diagram for the counter. The value of Q0 toggles once each clock cycle. The
change takes place shortly after the positive edge of the Clock signal. The delay is caused by the propagation
delay through the flip-flop. Since the second flip-flop is clocked by Q0, the value of Q1 changes shortly after
the negative edge of the Q0 signal. Similarly, the
value of Q2 changes shortly after the negative edge of the Q1 signal. If we look at the values Q2Q1Q0 as the
count, then the timing diagram indicates that the counting sequence is 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so on.
This circuit is a modulo-8 counter. Because it counts in the upward direction, we call it an up-counter.
Figure 1: 3 bit Asynchronous counter and its timing diagram
Synchronous counter
In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the
input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The most important advantage
of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in
parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the
corresponding ripple counter.
Table 1 shows the contents of a four-bit up-counter for eight consecutive clock cycles, assuming that the
count is initially 0. Observing the pattern of bits in each row of the table, it is apparent that bit Q0 changes on
each clock cycle. Bit Q1 changes only when Q0 = 1. Bit Q2 changes only when both Q1 and Q0 are equal to
1. In general, for an n-bit up-counter, a given flip-flop changes its state only when all the preceding flip-flops
are in the state Q = 1.
T0 = 1
Table 1:
The Circuit diagram of a four-bit counter based on these expressions is given in Figure 9.2a. Figure 9.2b gives
a timing diagram. It shows that the circuit behaves as a modulo-16 up- counter. Because all changes take place
with the same delay after the active edge of the Clock signal, the circuit is called a synchronous counter.
Figure 2a: A four-bit Synchronous Up Counter
Figure 2b: The timing diagram of a four-bit Synchronous Up Counter
Pin Configuration of 74LS76 and 7408
There are 2 J-K Flip Flops in one IC. Here is the pin configuration of the IC 74LS76:
Figure 3: IC 74LS76
IC 7408 contains 4 AND gates in it. The pin configuration is shown below:
Figure 4: IC 7408
Fig 5: 3 bit Asynchronous Counter
Fig 6: 3 bit Synchronous Counter
Apparatus:
Model
SL. Name Picture Quantity Remarks
number
Digital
AL-E139 Was not in good condition.
1 trainer 1
Had to change it.
board
2 IC 4
74LS76 Good condition
JK Flip Flop
3 1
IC 7408 Was not in good condition.
AND Gate Had
to change one of it.
4 Power 1 Good condition
supply
Connecting multiple
5 wires Good condition
Experimental Procedure:
Part 1: 3-bit Asynchronous Counter
1. The circuit was designed on the bread board as shown in Figure 9.5.
2. The trainer signal generator was used for the clock pulse and power supply for biasing the
Flip Flops.
3. Observe The output results were observed, recorded and also some pictures were taken for lab report.
Part 2: 4 bit synchronous Counter
1. The circuit was designed on the bread board as shown in Figure 9.5.
2. The trainer signal generator was used for the clock pulse and power supply for biasing the
Flip Flops.
3. Observe The output results were observed, recorded and also some pictures were taken for lab report.
Hardware Implementation:
3- bit Asynchronous counter
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
4-bit synchronous counter
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
Figure 9: output 8
Figure 10: output 9
Simulation (by using Ni Multism-13):
3 bit Asynchronous counter:
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
4 bit Synchronous counter:
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
Figure 9: output 8 Figure 10: output 9
Figure 11: output A Figure 12: output B
Figure 13: output C Figure 14: output D
Figure 14: output E Figure 16: output F
Discussion:
In this experiment, we tried to implement synchronous and asynchronous counter by using j-k flipflop both via
hardware implementation as well as simulation. We connected all the components correctly by maintaining
correct polarity. The data findings in the simulation suggest that the implemented 3-Bit counter was negative
edged. Due to limitations in the lab the triggering edge was not determine-able. The 3-Bit counter started from
BCD-0 and counted to BCD-7 and then it recycled and repeated. The 4-bit counter started from BCD-0 and
counted up to BCD - 15 and then it recycled and repeated. N-bit counter counts total 2º numbers.
Conclusion:
The objective of the experiment was to implement counters using Flip Flops. The implemented circuits Indeed count to
certain bit and then recycles and repeats itself over and over. So, the counters' implementation was done correctly, and the
experiment was concluded successfully.
Questions with answers for report writing:
1. Design a 4 bit Asynchronous Up- Counter.
A 4 bit Asynchronous up counter with all outputs:
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
Figure 9: output 8 Figure 10: output 9
Figure 11: output A Figure 12: output B
Figure 13: output C Figure 14: output D
Figure 14: output E Figure 16: output F
2. Design a 4 bit Synchronous Up- Counter.
A 4 bit synchronous up counter with all outputs:
Figure 1: output 1 Figure 2: output 2
Figure 3: output 3 Figure 4: output 4
Figure 5: output 5 Figure 6: output 6
Figure 7: output 7 Figure 8: output 8
Figure 9: output 9 Figure 10: output A
Figure 11: output B Figure 12: output C
Figure 13: output D Figure 14: output E
3. Design a 3 bit Asynchronous down counter. A 3 bit
asynchronous down counter with all outputs:
Figure 1: output 7 Figure 2: output 6
Figure 3: output 6 Figure 4: output 5
Figure 5: output 3 Figure 6: output 2
Figure 7 : output 1 Figure 8: output 0
4. Design a Mod 10 Synchronous up counter.
A mod 10 Synchronous counter with all outputs:
Figure 1: output 0 Figure 2: output 1
Figure 3: output 2 Figure 4: output 3
Figure 5: output 4 Figure 6: output 5
Figure 7: output 6 Figure 8: output 7
Figure 9: output 8 Figure 10: output 9
References:
[1] American International University Bangladesh (AIUB) digital logic circuit Lab Manual.
[2] www.tutorialspoint.com
[3] www.electronics-tutorials.ws
