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FSCQ1565RP
Green Mode Fairchild Power Switch (FPSTM) for
Quasi-Resonant Switching Converter
Features
• Optimized for Quasi-Resonant Converter (QRC) OUTPUT POWER TABLE
• Advanced Burst-Mode operation for under 1 W standby 230VAC ±15%(2) 85-265VAC
PRODUCT
power consumption Open Frame(1) Open Frame(1)
• Pulse by Pulse Current Limit (11.5A)
FSCQ0765RT 100 W 85 W
• Over load protection (OLP) - Auto restart
• Over voltage protection (OVP) - Auto restart FSCQ1265RT 170 W 140 W
• Abnormal Over Current Protection (AOCP) - Latch FSCQ1565RT 210 W 170 W
• Internal Thermal Shutdown (TSD) - Latch FSCQ1565RP 250 W 210 W
• Under Voltage Lock Out (UVLO) with hysteresis
• Low Startup Current (typical : 25uA)
• Low Operating Current (typical : 7mA) Table 1. Notes: 1. Maximum practical continuous power
• Internal High Voltage SenseFET in an open frame design at 50°C ambient. 2. 230 VAC or
100/115 VAC with doubler.
• Built-in Soft Start (20ms)
• Extended Quasi-resonant Switching for Wide Load Range

Application Typical Circuit

• CTV
• DVD Receiver Vo
• Audio Power Supply

AC
Description IN

In general, Quasi-Resonant Converter (QRC) shows lower

Drain
EMI and higher power conversion efficiency compared to the FSCQ1565RP

conventional hard switched converter with a fixed switching PWM

frequency. Therefore, it is well suited for applications that are Sync GND

sensitive to the noise, such as color TV and audio. The VFB Vcc
FSCQ1565RP is an integrated Pulse Width Modulation
(PWM) controller and Sense FET specifically designed for
Quasi-resonant off-line Switch Mode Power Supplies
(SMPS) with minimal external components. The PWM
controller includes integrated fixed frequency oscillator, under
voltage lockout, leading edge blanking (LEB), optimized gate
driver, internal soft start, temperature compensated precise
current sources for a loop compensation and self protection
circuitry. Compared with discrete MOSFET and PWM
controller solution, it can reduce total cost, component count, Figure 1. Typical Flyback Application
size and weight simultaneously increasing efficiency, produc-
tivity, and system reliability. This device is a basic platform
well suited for cost effective designs of Quasi resonant
switching flyback converters.

Rev.1.0.0
©2005 Fairchild Semiconductor Corporation
FSCQ1565RP

Internal Block Diagram

Sync Vcc Drain
5 3 1
+
Quasi-resonant +
(QR) switching fs
Threshold - controller
- 9V/15V
Soft start
4.6V/2.6V : Normal QR Vcc
3.0V/1.8V : Extended QR good

Burst mode Auxiliary

Controller OSC Vref Main bias
VBurst
Normal Burst
operation Switching Normal
Vref Vref Vref operation Internal
IBFB bias
IFB IB
Vcc

Idelay PWM
FB
S Q
4
2.5R Gate
R Q
R driver
LEB
600ns
VSD

Sync
S Q
AOCP
Vovp Q S
Vcc good R Q 2 GND
Q R TSD
Vocp
Power off Reset

Figure 2. Functional Block Diagram of FSCQ1565RP

2
 FSCQ1565RP

Pin Definitions

Pin Number Pin Name Pin Function Description

1 Drain High voltage power SenseFET drain connection.
2 GND This pin is the control ground and the SenseFET source.
This pin is the positive supply input. This pin provides internal operating
3 Vcc
current for both start-up and steady-state operation.
This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable
4 Vfb operation, a capacitor should be placed between this pin and GND. If the
voltage of this pin reaches 7.5V, the over load protection triggers resulting in
shutdown of the FPS.
This pin is internally connected to the sync detect comparator for quasi
resonant switching. In normal quasi-resonant operation, the threshold of the
5 Sync
sync comparator is 4.6V/2.6V. Meanwhile, the sync threshold is changed to
3.0V/1.8V in extended quasi-resonant operation.

Pin Configuration

TO-3PF-7L

5.Sync
4.Vfb
3.Vcc
2.GND

1.Drain

Figure 3. Pin Configuration (Top View)

3
FSCQ1565RP

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified)

Parameter Symbol Value Unit

(1)
Drain-Source (GND) Voltage VDSS 650 V
Drain-Gate Voltage (RGS=1MΩ) VDGR 650 V
Gate-Source (GND) Voltage VGS ±30 V
(2)
Drain Current Pulsed IDM 45 ADC
Single Pulsed Avalanche Energy (3) EAS 1050 mJ
Continuous Drain Current (Tc = 25°C) ID 8.3 ADC
Continuous Drain Current (TC=100°C) ID 5.5 ADC
Supply Voltage VCC 20 V
Vsync -0.3 to 13V V
Analog Input Voltage Range
VFB -0.3 to VCC V
Total Power Dissipation PD 98 W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature TA -25 to +85 °C
Storage Temperature Range TSTG -55 to +150 °C
Thermal Resistance Rthjc 1.28 °C/W
ESD Capability, HBM Model (All pins excepts 2.0
- kV
for Vfb) (Vfb=1.7kV)
ESD Capability, Machine Model (All pins 300
- V
excepts for Vfb) (Vfb=170V)

Notes:
1. Tj = 25°C to 150°C
2. Repetitive rating: Pulse width limited by maximum junction temperature
3. L = 21mH, VDD = 50V, RG = 25Ω, starting Tj = 25°C

4
 FSCQ1565RP

Electrical Characteristics (SenseFET Part)

(Ta=25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Drain-Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA 650 - - V
VDS = Max, Rating, VGS = 0V - - 200 µA
Zero Gate Voltage Drain Current IDSS VDS= 0.8*Max., Rating
- - 300 µA
VGS = 0V, TC = 85°C
Static Drain-source on Resistance (Note) RDS(ON) VGS = 10V, ID = 2.3A - 0.53 0.7 Ω
Input Capacitance Ciss - 3050 3965
VGS = 0V, VDS = 25V,
Output Capacitance Coss - 220 286 pF
f = 1MHz
Reverse Transfer Capacitance Crss - 40 52
Turn on Delay Time td(on) VDD= 0.5BVDSS, ID= 7.0A - 50 75
Rise Time tr (MOSFET switching - 130 179
times are essentially ns
Turn Off Delay Time td (off) independent of operating - 430 569
Fall Time tf temperature) - 135 186
Total Gate Charge VGS = 10V, ID = 7.0A,
Qg - 127 165
(Gate-Source+Gate-Drain) VDS = 0.5BVDSS (MOSFET
Gate-Source Charge Qgs Switching times are essentially - 16 21 nC
independent of operating
Gate-Drain (Miller) Charge Qgd temperature) - 52 68

Note:
1. Pulse test : Pulse width ≤ 300µS, duty ≤ 2%

5
FSCQ1565RP

Electrical Characteristics (Continued)

(Ta=25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

UVLO SECTION
Vcc Start Threshold Voltage VSTART VFB = GND 14 15 16 V
Vcc Stop Threshold Voltage VSTOP VFB = GND 8 9 10 V
SENSEFET SECTION
Drain To PKG Breakdown Voltage (Note4) BVpkg 60HZ AC, Ta = 25°C 3500 - - V
Drain To Source Breakdown Voltage BVdss Ta = 25°C 650 - - V
Drain To Source Leakage Current Idss Vdrain = 400V, Ta = 25°C - - 200 uA
OSCILLATOR SECTION
Initial Frequency FOSC - 18 20 22 kHz
Voltage Stability FSTABLE 12V ≤ Vcc ≤ 23V 0 1 3 %
Temperature Stability (Note2) ∆FOSC -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 %
Maximum Duty Cycle DMAX - 92 95 98 %
Minimum Duty Cycle DMIN - - - 0 %
FEEDBACK SECTION
Feedback Source Current IFB VFB = 0.8V 0.5 0.65 0.8 mA
Shutdown Feedback Voltage VSD Vfb ≥ 6.9V 7.0 7.5 8.0 V
Shutdown Delay Current IDELAY VFB = 5V 4 5 6 µA
PROTECTION SECTION
Over Voltage Protection VOVP Vsync ≥ 11V 11 12 13 V
Over Current Latch Voltage (Note2) VOCL - 0.9 1.0 1.1 V
Thermal Shutdown Temp (Note4) TSD - 140 - °C

Note:
1. These parameters is the current flowing in the Control IC.
2. These parameters, although guaranteed, are tested only in EDS (wafer test) process.
3. These parameters indicate Inductor Current.
4. These parameters, although guaranteed at the design, are not tested in mass production.

6
 FSCQ1565RP

Electrical Characteristics (Continued)

(Ta=25°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Sync SECTION
Sync Threshold in normal QR (H) VSH1 Vcc = 16V, Vfb = 5V 4.2 4.6 5.0 V
Sync Threshold in normal QR (L) VSL1 Vcc = 16V, Vfb = 5V 2.3 2.6 2.9 V
Sync Threshold in extended QR (H) VSH2 Vcc = 16V, Vfb = 5V 2.7 3.0 3.3 V
Sync Threshold in extended QR (L) VSL2 Vcc = 16V, Vfb = 5V 1.6 1.8 2.0 V
Extended QR enable frequency FSYH - 90 - kHz
Extended QR disable frequency FSYL - 45 - kHz
BURST MODE SECTION
Burst Mode Enable Feedback Voltage VBEN 0.25 0.40 0.55 V
Burst Mode Feedback Source Current IBFB 60 100 140 uA
Burst Mode switching Time TBS VFB = 0V 1.2 1.4 1.6 ms
Burst Mode Hold Time TBH VFB = 0V 1.2 1.4 1.6 ms
SOFTSTART SECTION
Soft start Time (Note2) TSS 18 20 22 ms
CURRENT LIMIT(SELF-PROTECTION)SECTION
Peak Current Limit (Note3) ILIM - 10.12 11.5 12.88 A
Burst Mode Peak Current Limit (Note4) IBPK - 0.6 1.0 1.4 A
TOTAL DEVICE SECTION
Startup Current ISTART VCC = VSTART-0.1V - 25 50 uA
Sustain Latch Current ISL VCC = VSTOP-0.1V - 50 100 uA
Operating Supply Current (Note1)
- In normal operation IOP Vfb = 2V, VCC = 18V - 7 9 mA
- In burst mode (without switching) IOB Vfb = GND, VCC = 18V - 0.25 0.50 mA

Note:
1. These parameters is the current flowing in the Control IC.
2. These parameters, although guaranteed, are tested only in EDS (wafer test) process.
3. These parameters indicate Inductor Current.
4. These parameters, although guaranteed at the design, are not tested in mass production.

7
FSCQ1565RP

Comparison Between KA5Q1565RF and FSCQ1565RP

Function KA5Q1565RF FSCQ1565RP FSCQ1565RP Advantages

Startup Current Max. 200uA Max. 50uA Lower standby power consumption

Operating supply Current Typ. 10mA Typ. 7mA Operating current is reduced in burst
operation to minimize standby power
consumption
- Normal operation : 7mA
- Burst mode with switching : 7mA
- Burst mode without switching : 0.25mA

Switching in Burst mode Quasi-resonant Fixed frequency

switching switching (20kHz)

Output regulation in Vcc control with Output voltage Easy to determine the output voltage in the
standby mode hysteresis feedback control standby mode

Output Voltage drop in about half Any level Lower power consumption in the standby
burst mode mode through larger output voltage drop

Primary side regulation Available N/A

Soft start N/A Available Internal soft-start (20ms)

Extended Quasi- N/A Available - Guarantees wide load range

resonant switching - Improved efficiency at high line input
Package Type TO-3PF-5L TO-3PF-7L

8
 FSCQ1565RP

Electrical characteristics

Operating Supply Current Burst-mode Supply Current( Non-Switching)

1.2 1.4
Normalized to 25℃

Normalized to 25℃
1.2

1.0 1.0

0.8

0.8 0.6
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃ ]

Start-Up Current Start Threshold Voltage

1.4 1.10
Normalized to 25℃
Normalized to 25℃

1.2 1.05

1.0 1.00

0.8 0.95

0.6 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃ ]

Stop Threshold Voltage Initial Frequency

1.10 1.10
Normalized to 25℃
Normalized to 25℃

1.05 1.05

1.00 1.00

0.95 0.95

0.90 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃]

9
FSCQ1565RP

Electrical characteristics (Continued)

Maximum Duty Cycle Over Voltage Protection

1.10 1.10

Normalized to 25℃
1.05 1.05
Normalized to 25℃

1.00 1.00

0.95 0.95

0.90 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ]
Temp[℃ ]

Shutdown Delay Current Shutdown Feedback Voltage

1.2 1.10

1.1
Normalized to 25℃

1.05
Normalized to 25℃

1.0 1.00

0.9 0.95

0.8 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃ ]

Feedback Source Current Burst_mode Feedback Source Current

1.2 1.2
Normalized to 25℃

1.1 1.1
Normalized to 25℃

1.0 1.0

0.9 0.9

0.8 0.8
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃ ]

10
 FSCQ1565RP

Electrical characteristics (Continued)

Feedback Offset Voltage Burst_Mode Enable Feedback Voltage

1.4
1.4

1.2

Normalized to 25℃
1.2
Normalized to 25℃

1.0 1.0

0.8 0.8

0.6 0.6
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃]

Sync. Threshold in Normal QR(H) Sync. Threshold in Normal QR(L)

1.10 1.10
Normalized to 25℃

1.05 1.05
Normalized to 25℃

1.00 1.00

0.95 0.95

0.90 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃] Temp[℃ ]

Sync. Threshold in Extended QR(H) Sync. Threshold in Extended QR(L)

1.10 1.10
Normalized to 25℃

1.05
Normalized to 25℃

1.05

1.00 1.00

0.95 0.95

0.90 0.90
-50 0 50 100 150 -50 0 50 100 150
Temp[℃ ] Temp[℃ ]

11
FSCQ1565RP

Electrical characteristics (Continued)

Extended QR Enable Freqency Extended QR Disable Frequency

1.10 1.10
Normalized to 25℃
℃

1.05 1.05

Normalized to 25℃
℃
1.00 1.00

0.95
0.95

0.90
-50 0 50 100 150 0.90
℃
Temp[℃ -50 0 50 100 150
] ℃]
Tem p[℃

Pulse-by-pulse Current Limit Maximum Safe Operating Aree

1.10 10
2

Operation in This Area

is Limited by R DS(on)
Normalized to 25℃

100 us
℃

1.05 10
1
1 ms
ID, Drain Current [A]

10 ms
DC
0
1.00 10

? Notes :
-1
0.95 10 o
1. T C = 25 C
o
2. T J = 150 C
3. Single Pulse

-2
10
0.90 10
0
10
1 2
10 10
3

-50 0 50 100 150

VDS, Drain-Source Voltage [V]
[℃
℃]]
Temp[℃

Transieus Thermal Response Maximum Avalanch Energy

0
10 1200

1000
AVALANCHE ENERGY, EAS[mJ]
Z? JC(t), Thermal Response

D=0.5
800
? Notes :
-1 1. Z? JC(t) = 0.46 ? /W Max.
10 0.2 2. Duty Factor, D=t1/t2
3. TJM - TC = PDM * Z? JC(t) 600
0.1

0.05 400

0.02
0.01 200
-2
10
single pulse
0
-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10 25 50 75 100 125 150
o
t1, Square Wave Pulse Duration [sec] Initial Junction Temperature, TJ [ C]

12
 FSCQ1565RP

Functional Description The minimum average of the current supplied from the AC is
given by
1. Startup : Figure 4 shows the typical startup circuit and
transformer auxiliary winding for FSCQ1565RP application.
min
Before FSCQ1565RP begins switching, FSCQ1565RP avg  2 ⋅ V ac V start 1
I sup =  ----------------------------- - ⋅ ----------
- – -------------
consumes only startup current (typically 25uA) and the  π 2  R str
current supplied from the AC line charges the external
capacitor (Ca1) that is connected to the Vcc pin. When Vcc
reaches start voltage of 15V (VSTART), FSCQ1565RP begins where Vacmin is the minimum input voltage, Vstart is the
switching, and the current consumed by FSCQ1565RP FSCQ1565RP start voltage (15V) and Rstr is the startup
increases to 4mA. Then, FSCQ1565RP continues its normal resistor. The startup resistor should be chosen so that Isupavg
switching operation and the power required for this device is is larger than the maximum startup current (50uA).
supplied from the transformer auxiliary winding, unless Vcc Once the resistor value is determined, the maximum loss in
drops below the stop voltage of 9V (VSTOP). To guarantee the startup resistor is obtained as
the stable operation of the control IC, Vcc has under voltage
lockout (UVLO) with 6V hysteresis. Figure 5 shows the max 2 2 max
relation between the FSCQ1565RP operating supply current 1  ( V ac ) + V start 2 2 ⋅ V start ⋅ V ac 
Loss = ---------- ⋅  -------------------------------------------------- -
- – -----------------------------------------------------
and the supply voltage (Vcc). R str  2 π 

where Vacmax is the maximum input voltage. The startup

resistor should have proper rated dissipation wattage.

C DC
2. Synchronization : FSCQ1565RP employs quasi-resonant
switching technique to minimize the switching noise and loss.
In this technique, a capacitor (Cr) is added between the
MOSFET drain and source as shown in Figure 6. The basic
1N4007
waveforms of quasi-resonant converter are shown in Figure
AC line
(V acmin - V acmax) Isup 7. The external capacitor lowers the rising slop of drain
voltage to reduce the EMI caused when the MOSFET turns
Rstr off. In order to minimize the MOSFET switching loss, the
MOSFET should be turned on when the drain voltage reaches
Da
Vcc its minimum value as shown in Figure 7.
FSCQ1565RP

C a1 C a2

+ Np
C DC V DC
- Ns
Lm Vo
Figure 1. Startup circuit
Drain

Cr +
Ids V ds
Icc Sync
-

GND

V co Da
V cc
R cc Na
C a1 C a2 D SY
4mA

R SY1

Power Up
Power Down
C SY R SY2
25uA
Vcc
Vstop=9V Vstart=15V Vz

Figure 3. Synchronization circuit

Figure 2. Relation between operating supply current and
Vcc voltage

13
FSCQ1565RP

Vds
MOSFET MOSFET
off on

Vgs 2V R O

TQ
VRO
Vs ync
VRO V sypk
Vds
VDC
Vrh (4 .6V)

Vrf (2 .6V)
TR
Ids Ipk MOS FET Gate

ON ON
Figure 4. Quasi-resonant operation waveforms

Figure 5. Normal quasi-resonant operation waveforms

The minimum drain voltage is indirectly detected by
monitoring the Vcc winding voltage as shown in Figure 6
and 8. The voltage divider RSY1 and RSY2 should be chosen so Switching
that the peak voltage of sync signal (Vsypk) is lower than the frequency
OVP voltage (12V) in order to avoid triggering OVP in
Extended QR operation
normal operation. It is typical to set Vsypk to be lower than
OVP voltage by 3-4 V. In order to detect the optimum time
to turn on MOSFET, the sync capacitor (CSY) should be 90kHz
determined so that TR is the same with TQ as shown in Figure Normal QR operation

8. The TR and TQ are given as, respectively

45kHz
V co R SY2
TR = R SY2 ⋅ C SY ⋅ ln  --------- ⋅ -----------------------------------
 2.6 R SY1 + R SY2

T Q = π ⋅ L m ⋅ C eo
Output power

N a ⋅ ( V o + V FO ) Figure 6. Extended quasi-resonant operation

V co = ----------------------------------------
- – V Fa
Ns
In general, quasi-resonant converter has a limitation in a
wide load range application, since the switching frequency
where Lm is the primary side inductance of the transformer, increases as the output load decreases, resulting in a severe
Ns and Na are the number of turns for the output winding switching loss in the light load condition. In order to get over
and Vcc winding, respectively, VFo and VFa are the diode this limitation, FSCQ1565RP employs extended quasi-
forward voltage drops of the output winding and Vcc resonant switching operation. Figure 9 shows the mode
winding, respectively, and Ceo is the sum of the output change between normal quasi-resonant operation and
capacitance of MOSFET and external capacitor Cr. extended quasi-resonant operation. In the normal quasi-
resonant operation, the FSCQ1565RP enters into the
extended quasi-resonant operation when the switching
frequency exceeds 90kHz as the load reduces. Then, the
MOSFET is turned on, when the drain voltage reaches the
second minimum level as shown in Figure 10, which reduces
the switching frequency.

14
 FSCQ1565RP

Once FSCQ1565RP enters into extended quasi-resonant internal Sense FET is turned on, there usually exists a high
operation, the first sync signal is ignored. After the first sync current spike through the Sense FET, caused by external
signal is applied, the sync threshold levels are changed from resonant capacitor across the MOSFET and secondary-side
4.6V and 2.6V to 3V and 1.8V, respectively, and the rectifier reverse recovery. Excessive voltage across the
MOSFET turn-on time is synchronized to the second sync Rsense resistor would lead to incorrect feedback operation in
signal. The FSCQ1565RP goes back to its normal quasi- the current mode PWM control. To counter this effect, the
resonant operation when the switching frequency reaches FSCQ1565RP employs a leading edge blanking (LEB)
45kHz as the load increases. circuit. This circuit inhibits the PWM comparator for a short
time (TLEB) after the Sense FET is turned on.
Vds

Vcc Vref
2VRO
Idelay IFB

Vo Vfb SenseFET
4 OSC
H11A817A D1 D2
CB 2.5R

+ Gate
Vsync Vfb* R driver
KA431 -

4.6V
3V OLP Rsense
VSD
2.6V
1.8V

MOSFET Gate Figure 8. Pulse width modulation (PWM) circuit

4. Protection Circuit : The FSCQ1565RP has several self

ON ON
protective functions such as over load protection (OLP),
abnormal over current protection (AOCP), over voltage
protection (OVP) and thermal shutdown (TSD). OLP and
OVP are auto-restart mode protection, while TSD and
Figure 7. Extended quasi-resonant operation waveforms
AOCP are latch mode protection. Because these protection
circuits are fully integrated into the IC without external
3. Feedback Control : FSCQ1565RP employs current mode components, the reliability can be improved without
control, as shown in Figure 11. An opto-coupler (such as the increasing cost.
H11A817A) and shunt regulator (such as the KA431) are -Auto-restart mode protection: Once the fault condition is
typically used to implement the feedback network. detected, switching is terminated and the Sense FET remains
Comparing the feedback voltage with the voltage across the off. This causes Vcc to fall. When Vcc falls down to the
Rsense resistor plus an offset voltage makes it possible to under voltage lockout (UVLO) stop voltage of 9V, the
control the switching duty cycle. When the reference pin protection is reset and FSCQ1565RP consumes only startup
voltage of the KA431 exceeds the internal reference voltage current (25uA). Then, Vcc capacitor is charged up, since the
of 2.5V, the H11A817A LED current increases, thus pulling current supplied through the startup resistor is larger than the
down the feedback voltage and reducing the duty cycle. This current that FPS consumes. When Vcc reaches the start
event typically happens when the input voltage is increased voltage of 15V, FSCQ1565RP resumes its normal operation.
or the output load is decreased. If the fault condition is not removed, the SenseFET remains
3.1 Pulse-by-pulse current limit: Because current mode off and Vcc drops to stop voltage again. In this manner, the
control is employed, the peak current through the Sense FET auto-restart can alternately enable and disable the switching
is limited by the inverting input of PWM comparator (Vfb*) of the power Sense FET until the fault condition is
as shown in Figure 11. The feedback current (IFB) and eliminated (see Figure 12).
internal resistors are designed so that the maximum cathode -Latch mode protection: Once protection triggers,
voltage of diode D2 is about 2.8V, which occurs when all IFB switching is terminated and the Sense FET remains off until
flows through the internal resistors. Since D1 is blocked the AC power line is un-plugged. Then, Vcc continues
when the feedback voltage (Vfb) exceeds 2.8V, the charging and discharging between 9V and 15V. The latch is
maximum voltage of the cathode of D2 is clamped at this reset only when Vcc is discharged to 6V by un-plugging the
voltage, thus clamping Vfb*. Therefore, the peak value of Ac power line.
the current through the Sense FET is limited.
3.2 Leading edge blanking (LEB) : At the instant the

15
FSCQ1565RP

Fault
occurs Fault V FB Over load protection
Vds Power
removed
on 7.5V

Vcc 2.8V

15V
T12= CB*(7.5-2.8)/Idelay
9V

T1 T2 t

Figure 10. Over load protection

Iop
4mA
4.2 Abnormal Over Current Protection (AOCP) : When
25uA
the secondary rectifier diodes or the transformer pins are
shorted, a steep current with extremely high di/dt can flow
t
Normal Fault Normal through the SenseFET during the LEB time. Even though the
operation situation operation FSCQ1565RP has OLP (Over Load Protection), it is not
Figure 9. Auto restart mode protection enough to protect the FSCQ1565RP in that abnormal case,
since sever current stress will be imposed on the SenseFET
until OLP triggers. The FSCQ1565RP has an internal AOCP
(Abnormal Over Current Protection) circuit as shown in
Figure 14. When the gate turn-on signal is applied to the
4.1 Over Load Protection (OLP) : Overload is defined as power Sense FET, the AOCP block is enabled and monitors
the load current exceeding its normal level due to an the current through the sensing resistor. The voltage across
unexpected abnormal event. In this situation, the protection the resistor is then compared with a preset AOCP level. If
circuit should trigger in order to protect the SMPS. However, the sensing resistor voltage is greater than the AOCP level,
even when the SMPS is in the normal operation, the over the set signal is applied to the latch, resulting in the
load protection circuit can be triggered during the load shutdown of SMPS. This protection is implemented in latch
transition. In order to avoid this undesired operation, the mode.
over load protection circuit is designed to trigger after a
specified time to determine whether it is a transient situation
or an overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current through
the Sense FET is limited, and therefore the maximum input 2.5R
OSC
power is restricted with a given input voltage. If the output S Q
PWM
consumes more than this maximum power, the output Gate
R Q driver
voltage (Vo) decreases below the set voltage. This reduces
the current through the opto-coupler LED, which also R LEB
reduces the opto-coupler transistor current, thus increasing
the feedback voltage (Vfb). If Vfb exceeds 2.8V, D1 is
Rsense
blocked and the 5uA current source starts to charge CB +
2
slowly up to Vcc. In this condition, Vfb continues increasing AOCP
GND
until it reaches 7.5V, when the switching operation is Vaocp
-

terminated as shown in Figure 13. The delay time for

shutdown is the time required to charge CB from 2.8V to
7.5V with 5uA. In general, a 20 ~ 50 ms delay time is typical Figure 11. AOCP block
for most applications. This protection is implemented in auto
restart mode.
4.3 Over voltage Protection (OVP) : If the secondary side
feedback circuit were to malfunction or a solder defect
caused an open in the feedback path, the current through the
opto-coupler transistor becomes almost zero. Then, Vfb
climbs up in a similar manner to the over load situation,

16
 FSCQ1565RP

forcing the preset maximum current to be supplied to the

SMPS until the over load protection triggers. Because more
energy than required is provided to the output, the output stby
V o2 = V Z + 0.7 + 2.5
voltage may exceed the rated voltage before the over load
protection triggers, resulting in the breakdown of the devices
in the secondary side. In order to prevent this situation, an
over voltage protection (OVP) circuit is employed. In VO2
general, the peak voltage of the sync signal is proportional to
the output voltage and the FSCQ1565RP uses sync signal Linear Micom

instead of directly monitoring the output voltage. If sync VO1 (B+) Regulator

signal exceeds 12V, an OVP is triggered resulting in a RD Dz

shutdown of SMPS. In order to avoid undesired triggering of Rbias
R3
OVP during normal operation, the peak voltage of sync R1
signal should be designed to be below 12V. This protection CF RF D1
is implemented in auto restart mode. Q1
C Picture ON
R
4.4 Thermal Shutdown (TSD) : The SenseFET and the KA431
A R2
control IC are built in one package. This makes it easy for
the control IC to detect the abnormal over temperature of the
SenseFET. When the temperature exceeds approximately
150°C, the thermal shutdown triggers. This protection is Figure 12. Typical feedback circuit to drop output voltage
implemented in latch mode. in standby mode

5. Soft Start : The FSCQ1565RP has an internal soft start

circuit that increases PWM comparator inverting input Figure 16 shows the burst mode operation waveforms. When
voltage together with the SenseFET current slowly after it the picture ON signal is disabled, Q1 is turned off and R3
starts up. The typical soft start time is 20msec. The pulse and Dz are connected to the reference pin of KA431 through
width to the power switching device is progressively D1. Before Vo2 drops to Vo2stby, the voltage on the reference
increased to establish the correct working conditions for pin of KA431 is higher than 2.5V, which increases the
transformers, inductors, and capacitors. It also helps to current through the opto LED. This pulls down the feedback
prevent transformer saturation and reduce the stress on the voltage (VFB) of FSCQ1565RP and forces FSCQ1565RP to
secondary diode during startup. For a fast build up of the stop switching. If the switching is disabled longer than
output voltage, an offset is introduced in the soft-start 1.4ms, FSCQ1565RP enters into burst operation and the
reference current. operating current is reduced from 4mA (IOP) to 0.35mA
(IOB). Since there is no switching, Vo2 decrease until it
6. Burst operation : In order to minimize the power reaches Vo2stby. As Vo2 reaches Vo2stby, the current through
consumption in the standby mode, FSCQ1565RP employs the opto LED decreases allowing the feedback voltage to
burst operation. Once FSCQ1565RP enters into burt mode, rise. When the feedback voltage reaches 0.4V, FSCQ1565RP
FSCQ1565RP allows all output voltages and effective resumes switching with a predetermined peak drain current
switching frequency to be reduced. Figure 15 shows the of 0.9A. After burst switching for 1.4ms, FSCQ1565RP
typical feedback circuit for C-TV applications. In normal stops switching and checks the feedback voltage. If the
operation, the picture on signal is applied and the transistor feedback voltage is below 0.4V, FSCQ1565RP stops
Q1 is turned on, which de-couples R3, Dz and D1 from the switching until the feedback voltage increases to 0.4V. If the
feedback network. Therefore, only Vo1 is regulated by the feedback voltage is above 0.4V, FSCQ1565RP goes back to
feedback circuit in normal operation and determined by R1 the normal operation.
and R2 as

R1 + R2
= 2.5 ⋅  ---------------------
norm
V o1
 R2 

In standby mode, the picture on signal is disabled and the

transistor Q1 is turned off, which couples R3, Dz and D1 to
the reference pin of KA431. Then, Vo2 is determined by the
zener diode breakdown voltage. Assuming that the forward
voltage drop of D1 is 0.7V, Vo2 in standby mode is approxi-
mately given by

17
FSCQ1565RP

(a) (b) (c)

Vo2 norm

V o2 stby

V FB

0.4V

Iop
I OP (4m A)

I OB (0.35m A)

Vds

Picture On Picture Off Picture On

Burst Mode

VFB 0.4V 0.4V 0.4V

0.3V

Vds

1.4ms 1.4ms 1.4ms

0.9A 0.9A
Ids

(a) M ode change to Burst operation (b) Burst operation (c) M ode change to Normal operation

Figure 13. Waveforms of burst operation

18
 FSCQ1565RP

Typical application circuit

Application Output power Input voltage Output voltage (Max current)

8.5V (1A)
Universal input 15V (1A)
C-TV 210W
(85-265Vac) 126V (0.9A)
24V (2A)

Features
• High efficiency (>80% at 85Vac input)
• Wider load range through the extended quasi-resonant operation
• Low standby mode power consumption (<1W)
• Low component count
• Enhanced system reliability through various protection functions
• Internal soft-start (20ms)

Key Design Notes

• 24V output is designed to drop to around 7V in standby mode

1. Schematic

T1 D205
EER4942 EGP20D
15V, 1A
RT101 10
1
C204
5D-11
C210 1000uF
470pF 35V
C102 3 11 1kV
470uF D204
400V R102 BEAD101 EGP20D
Ω
150kΩ 4 8.5V, 1A
R101 0.25W 13
BD101 Ω
100kΩ C107 C205
R106 C104 1nF C209 1000uF
0.25W D105
Ω 10uF
1kΩ 1kV 470pF 35V
1 1N4937 12 1kV
1W 50V
Drain
SYNC D202
3 Vcc IC101 5 EGP30J
ZD102 FSCQ1565RP 140V, 0.9A
D106 R104 D103 R103 6 14 L202
18V GND FB Ω 1N4937 5.1Ω
1.5kΩ Ω C201 BEAD C202
1N4148
1W 0.25W 0.25W 15 C207 220uF 100uF
2 4
470pF 160V 160V
16 1kV
C105
C103 C106 R105 2.7nF D203
10uF 47nF 470ΩΩ 50V EGP30D
50V 50V 0.25W 24V, 2A
17
7 C203
C208 2200uF
LF101 470pF 35V
18 1kV

VR201
R201
Ω
30kΩ
Ω
1kΩ
OPTO101 0.25W
817A ZD201
R202 5.1V
C101 C206 R203 R205 0.5W
Ω
1kΩ
330nF 22nF 39kΩΩ Ω D201
240kΩ R208
0.25W SW201
275VAC 50V 0.25W 0.25W 1N4148 1kΩΩ R207
FUSE 0.25W Ω
5.1kΩ
250V
C301 0.25W
5.0A Q202
3.3nF Q201 R204 R206
KSC945
KA431 Ω
4.7kΩ 10kΩΩ
LZ 0.25W 0.25W

19
FSCQ1565RP

2. Transformer Schematic Diagram

EE R 4245
EER4942
Np1 1 18

N 24V
2 17 Na

N 15V
3 16
Np2
N140V /2/2 N8.5V
N 125V
4 15
N 140V /2
NN140V
125V /2
/2
5 14
NP 2

6 13 N 140V /2

N8.5V
NP 1
7 12
Na
N24
8 11

N15V
9 10

3.Winding Specification

No Pin (s→f) Wire Turns Winding Method

φ
N24 18 - 17 0.65 × 2 7 Space Winding
φ
Np1 1-3 0.08 × 20 × 2 18 Center Winding
N140V/2 16 - 15 0.08φ × 20 × 2 20 Center Winding
Np2 3-4 0.08φ × 20 × 2 18 Center Winding
φ
N140V/2 15 - 14 0.08 × 20 × 2 20 Center Winding
N8.5V 12 - 13 0.6φ ×1 3 Space Winding
φ
N15V 11 - 10 0.4 × 2 5 Space Winding
φ
Na 7-6 0.3 × 1 12 Space Winding
4.Electrical Characteristics

Pin Specification Remarks

Inductance 1-4 225uH ± 5% 1kHz, 1V
Leakage Inductance 1-4 10uH Max 2nd all short

5. Core & Bobbin

Core : EER 4942
Bobbin : EER4942(18Pin)
Ae : 231 mm2

20
 FSCQ1565RP

6.Demo Circuit Part List

Part Value Note Part Value Note

Fuse C210 470pF / 1kV Ceramic Capacitor
FUSE 250V / 5A C301 3.3nF / 1kV AC Ceramic Capacitor
NTC Inductor
RT101 5D-11 BEAD101 BEAD
Resistor BEAD201 5uH 3A
R101 100kΩ 0.25 W Diode
R102 150kΩ 0.25 W D101 1N4937 1A, 600V
R103 5.1Ω 0.25 W D102 1N4937 1A, 600V
R104 1.5kΩ 0.25 W D103 1N4148 0.15A, 50V
R105 470Ω 0.25 W D104 Short
R106 1kΩ 1W D105 Open
R107 Open ZD101 1N4746 18V, 1W
R201 1kΩ 0.25 W ZD102 Open
R202 1kΩ 0.25 W ZD201 1N5231 5.1V, 0.5W
R203 39kΩ 0.25 W D201 1N4148 0.15A, 50V
R204 4.7kΩ 0.25 W , 1% D202 EGP30J 3A, 600V
R205 240kΩ 0.25 W , 1% D203 EGP30D 3A, 200V
R206 10kΩ 0.25 W D204 EGP20D 2A, 200V
R207 5.1kΩ 0.25 W D205 EGP20D 2A, 200V
R208 1kΩ 0.25 W
VR201 30kΩ Bridge Diode
Capacitor BD101 GSIB660 6A, 600V
C101 330n/275Vac Box Capacitor Line Filter
C102 470uF / 400V Electrolytic LF101 14mH
C103 10uF / 50V Electrolytic Transformer
C104 10uF / 50V Electrolytic T101 EER4942
C105 2.7nF / 50V Film Capacitor Switch
C106 47nF / 50V Film Capacitor SW201 ON/OFF For MCU Signal
C107 1nF / 1kV Film Capacitor IC
C108 Open IC101 FSCQ1565RP TO220F-5L
C201 220uF / 200V Electrolytic OPT101 817A
C202 100uF / 200V Electrolytic Q201 KA431LZ TO-92
C203 2200uF / 35V Electrolytic Q202 KSC945
C204 1000uF / 35V Electrolytic
C205 1000uF / 35V Electrolytic
C206 22nF / 50V Film Capacitor
C207 470pF / 1kV Ceramic Capacitor
C208 470pF / 1kV Ceramic Capacitor
C209 470pF / 1kV Ceramic Capacitor

21
FSCQ1565RP

7. Layout

Figure 14. Layout Considerations for FSCQ1565RP

Figure 15. Layout Considerations for FSCQ1565RP

22
 FSCQ1565RP

Package Dimensions
Dimensions in Millimeters

TO-3PF-7L(Forming)
6.05
5.65
15.70 3.55
15.30 3.15
9.70
9.30 (1.65)

4.70
4.30

10.20
9.80

2.10
1.70

23.20
24.70 22.80
24.30

36.50
35.50
1.70
4.30 1.30
3.70
(1.00)

2.55
R0.90 2.15
MAX 1.00 3.65
3.05
12.00
11.00 R0.90 3.06
2.46
0.90
MAX 2.00 0.70 2.80
2.20 R0.90

5.30
4.70 0.80
2.54 0.50

1.50 3.48
2.88

4.50

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE DOES NOT COMPLY
TO ANY CURRENT PACKAGING STANDARD.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.

MKT-TO3PFC05revA

23
FSCQ1565RP

Ordering Information
Product Number Package Marking Code BVdss Rds(ON) Max.
FSCQ1565RPSYDTU TO-3PF-7L(Forming) CQ1565RP 650V 0.7 Ω
SYDTU : Forming Type

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support
perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

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1/11/05 0.0m 001

 2005 Fairchild Semiconductor Corporation