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ECE 5315: Project 3: Simulation of Pipelined Floating Point Processor Design: Pipelined FP Adder | PDF | Input/Output | Digital Electronics
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ECE 5315: Project 3: Simulation of Pipelined Floating Point Processor Design: Pipelined FP Adder

This document describes a project to simulate a pipelined floating point adder. The objective is to simulate the arithmetic pipeline of a TI-ASC processor by implementing only the adder portion. The simulation will take decimal numbers from a data file and compute their sum using a pipelined architecture. The pipeline consists of five stages - input, exponent subtract, align, normalize, and output. It must display the input and output of each stage, indicate which stages are empty/computing, and allow simulation via a button click or timer. The implementation and scheduling must be described in a report.

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Siddarth Venkatraman
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101 views3 pages

ECE 5315: Project 3: Simulation of Pipelined Floating Point Processor Design: Pipelined FP Adder

This document describes a project to simulate a pipelined floating point adder. The objective is to simulate the arithmetic pipeline of a TI-ASC processor by implementing only the adder portion. The simulation will take decimal numbers from a data file and compute their sum using a pipelined architecture. The pipeline consists of five stages - input, exponent subtract, align, normalize, and output. It must display the input and output of each stage, indicate which stages are empty/computing, and allow simulation via a button click or timer. The implementation and scheduling must be described in a report.

Uploaded by

Siddarth Venkatraman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 5315: Project 3

Simulation of Pipelined Floating Point Processor Design:


Pipelined FP Adder

1. Objective
The object of this project is to partially simulate implementation of the TI-ASC
arithmetic pipeline, i.e. only the adder portion. The given implementation is a hardware
simulation of the pipelined Floating Point (FP) adder that computes:

Sum = (a1 + a2 + … + a10)

where ai is decimal numbers given through a data file named “data.txt” which can be
downloaded from the provided link of this project.
Since this project is a hardware simulation, you should try your best to represent the
actual discrete components as closely as possible. For example, you can assume that adders and
multipliers are available for computing mantissa and exponents.

2. Simulation

The bit-widths of floating points for this project are defined as 32-bit mantissa and 8-bit
exponent. The exponent is encoded using excess-127 encoding. Next the pipeline stages are
described (please also refer to the handout).

Input

Exponent
Subtract

Align

Fraction Add

Normalize

Output
Reading the data from a file:
Please copy the “data.txt” file into your program “~\bin\Debug\” folder and then use the
following code to read in the data. You must add the “using Systems.IO” name space.
//read in test data from a file
StreamReader sr = new StreamReader(Application.StartupPath + @"\data.txt");
string txt = sr.ReadToEnd();
sr.Close(); //close the stream
// separate each data item
char[] delimeters = { ',', ' '};
string[] strArr = txt.Split(delimeters, StringSplitOptions.RemoveEmptyEntries);
//read the data in
float[] fdata = new float[strArr.Length];
for (int i = 0; i < fdata.Length; i++)
{
fdata[i] = Convert.ToSingle(strArr[i]);
}

You should schedule the pipeline inputs to efficiently compute the summation, i.e., to minimize
the latency. For example, you may first feed pairs: a1+a2, a3+a4, a5+a6, a7+a8, and a9+a10.
And then, feed the next level of addition pairs until it reaches to the final summation.

(1) Input stage: Convert two decimal numbers to two mantissa and exponent pairs.

(2) Exponent Subtract stage: Always subtract the smaller exponent from the larger exponent.

(3) Align stage: The small number mantissa is shifted to right the amount of the difference in
stage (2) before it is passed to the next stage.

(4) Normalize stage: Normalize and adjust the mantissa and exponent

(5) Output stage: Output the final summation mantissa and exponent.

The hardware consists of pipeline stages and a pipeline controller.

Requirements
1. Using textbox or label, show the input and output of each pipeline stage per pipeline clock
cycle.
2. Show which stage is empty and which stage is computing using background color changes of
the textbox or label.
3. Simulate the pipeline clock cycle through clicking of a button and also by a timer for an
automated run. Both options should be available.
4. Pipeline schedule should be visible, i.e., it should show the order of additions it is computing.
5. One of the requirements of the pipeline stages is a buffer for each stage so that the data can be
hold some cases more than one clock cycle before it is passed. Show this relation through GUI.
3. Check-off
Show the pipeline control and computation by a button and also automation by a timer to demo
your program. The better visualization will get a higher grade.

4. Report

1. Introduction
2. Your implementation of each pipeline stage and scheduling of the computation.
3. Conclusion
4. Code list

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