High-Speed Serial Interface
Circuits and Systems
Design Exercise 5
Phase Frequency Detector
High-Speed Circuits and Systems Lab., Yonsei University
Charge Pump PLL
ɸref up
ɸout
PFD down CP LF VCO
ɸdiv
Divider
VCO (Week 2-3)
- Generates the actual clock used by the system
Charge Pump (Week 4)
- Adjusts the frequency control signal of the VCO by charging and discharging the
loop filter using the up and down signals of the PFD.
PFD (Today)
- Compares the reference clock to the VCO clock to determine whether the charge
pump will charge or discharge the loop filter.
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Phase Frequency Detector
<PFD operation> <PFD structure>
Phase detector can’t detect frequency difference.
Using PFD, both phase lead/lag conditions and frequency lead/lag
conditions can be calculated.
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TSPC D flip flop
True single-phase clock DFF (Developed in the 80s’)
Using dynamic logic gate topology.
Widely used structure for high speed applications.
Detailed explanation
: B. Razavi, "TSPC Logic,“ IEEE Solid-State Circuits Magazine, Fall 2016
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TSPC DFF Schematic
– MOS Length
• 모두 180 nm로 고정
pmos2v pmos2v pmos2v pmos2v pmos2v
w = 9u w = 9u w = 9u w = 18u w = 18u
pmos2v nmos2v nmos2v
w = 9u w = 3u w = 3u
nmos2v nmos2v nmos2v nmos2v
w = 3u w = 3u w = 3u w = 6u
5 High-Speed Circuits and Systems Lab., Yonsei University
Simulation Setup
‘clk’ node
use ‘vpulse’
Voltage 1 = 0
Voltage 2 = 1.8
Period = 1/clk
delay time = delay
rise time = 1p
Fall time = 1p
Pulse width = 0.5/clk
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Simulation Setup
‘rstn’ node
use ‘vpulse’
Voltage 1 = 1.8
Voltage 2 = 0
Period = 500m
delay time = reset_start
rise time = 1p
Fall time = 1p
Pulse width = 250m
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Simulation Setup
‘D’ node
use ‘rand_bit_stream’
tperiod = 1/clk
seed = 1
vlogic_high = 1.8
vlogic_low = 0
tdel = 1p
trise = 1p
tfall = 1p
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Simulation Condition
• Simulation condition setting
– Choose analysis
– Analysis : tran
– transient sim. time = 5u
– Design variable :
– reset_start = 4u
– clk = 100M
– delay = 7.7777n
• check output node to plot
– Q
– clk
– D
– rstn
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Simulation result
clk
rstn rstn : 1 → 0
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Simulation result
D
clk
rstn rstn : 1 → 0
DFF reset
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Modified structure of TSPC for PFD
Precharge type PFD
Required MOS for sampler : 12 → 8
D + reset → set
Widely used for PFD design
Detailed explanation
: Sungjoon Kim et al, "A 960-Mb/s/pin interface for skew-
tolerant bus using low jitter PLL," IEEE Journal of Solid-State
Circuits, May 1997
12 High-Speed Circuits and Systems Lab., Yonsei University
Modified TSPC DFF Schematic
– MOS Length
• 모두 180 nm로 고정
pmos2v pmos2v pmos2v
w = 9u w = 9u w = 18u
pmos2v nmos2v
w = 9u w = 3u
nmos2v nmos2v nmos2v
w = 3u w = 3u w = 6u
13 High-Speed Circuits and Systems Lab., Yonsei University
Simulation Setup
‘clk_ref’ node
use ‘vpulse’
Voltage 1 = 0
Voltage 2 = 1.8
Period = 1/clk_ref
delay time = delay_ref
rise time = 1p
Fall time = 1p
Pulse width = 0.5/clk_ref
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Simulation Setup
‘clk_div’ node
use ‘vpulse’
Voltage 1 = 0
Voltage 2 = 1.8
Period = 1/clk_div
delay time = delay_div
rise time = 1p
Fall time = 1p
Pulse width = 0.5/clk_div
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Simulation Setup
‘nor_gate’
vlogic_high = 1.8
vlogic_low = 0
vtrans = 0.9
tdel = 1p
trise = 1p
tfall = 1p
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Simulation Condition
• Simulation condition setting
– Choose analysis
– Analysis : tran
– transient sim. time = 100n
– Design variable :
– clk_ref = 100M
– clk_div = 100M
– delay_ref = 0n / 1n
– delay_div = 1n / 0n
• check output node to plot
– clk_ref
– clk_div
– up
– down
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Simulation Condition
• Initial Condition
• Nodes
– SET = 1.8
– QB_ref 1.8
– QB_div = 1.8
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Phase lead
clk_ref = 100M
clk_div = 100M
delay_ref = 0n
delay_div = 1n
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Phase lag
clk_ref = 100M
clk_div = 100M
delay_ref = 1n
delay_div = 0n
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Frequency lead
clk_ref = 105M
clk_div = 100M
delay_ref = 0n
delay_div = 0n
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Frequency lag
clk_ref = 100M
clk_div = 105M
delay_ref = 0n
delay_div = 0n
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Dead zone of PFD
PFD cannot detect the phase difference in a certain area:
- Dead zone of PFD
Caused by finite rising/falling time of DFF output
The larger the dead zone, the worse the jiiter performance of the PLL.
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Dead zone of PFD
< delay= 1n > < delay= 5p >
PFD output can’t rise to logic high.
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Connect to Charge Pump
Invert up signal to upb
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Homework
Simulate Vcont with co-simulation of PFD and CP.
Use charge pump circuit made in DE 4th.
Loop filter for charge pump : 10p capacitor load
Initial Condition : Charge pump output (Vcont) = 0.9
Check for all conditions : Phase lead/lag, Frequency lead/lag
Deadline : 10/13 9:30
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