D/A and A/D Converters, VFC and FVC 6.1 Introduction ‘The primary objective of industrial process control is to control physical parameters such as temperature, pressure, flow rate, level, force, light intensity, and so on. The process control system is designed to maintain these parameters near some desired specific value. ‘As these parameters can change either spontaneously or because of external influences, we must constantly provide corrective action to keep these parameters constant or within the specified range. To control the process parameter, we must know the value of that parameter and hence it is necessary to measure that parameter. In general, a measurement refers to the transduction of the process parameter into some corresponding analog of the parameter, such as a pneumatic pressure, an electric voltage, or current. A transducer is a device that performs the initial measurement and energy conversion of a process parameter into analogous electrical or pneumatic information. Many times further transformation or signal enhancement may be required to complete the measurement function. Such processing is known as signal conditioning. Most of the information carrying signals such as voltage, current, charge, temperature, pressure and time are available in the analog form. However, for processing, transmission and storage purposes, it is often more convenient to express such signals in the digital form. When expressed in the digital form, they provide better accuracy and reduce noise. Moreover, the development in the microprocessor technology has made it compulsory to process data in the digital form. Since digital systems such as microprocessor use a binary system of ones and zeros, we have to convert signal from analog form to digital form, The circuit that performs this conversion is called an analog to digital (A/D) converter. Once the signal is measured it is used to * Compare with set value and determine the control signal in the process control system or © Generate desired output by processing the signal. The term digital signal processing, or DSP, is a very general term used to describe any system which accepts samples of a signal with an A/D converter, processes the samples with a microcomputer, and sends the computed result to a D/A converter or some other device. The Fig. 6.1 shows the basic elements of digital signal processing system. Most of (6-1)Analog and Digital Electronics 6-2 DIA and A/D Converters, VFC and FVC the signals generated are analog in nature. Hence these signals are converted to digital form by the analog to digital converter. Thus the A/D converter generates an array of samples and gives it to the digital signal processor. This array of samples (or sequence of samples) is the digital equivalent of input analog signal. It is called digital signal. The digital signal processor performs signal processing operations like filtering, multiplication, transformation, amplification etc. over this digital signal and generates another digital signal at its output. The digital signal processor can be a high speed digital computer and specially designed digital signal processor. Digital signal processors perform signal Processing operations with the help of the software, which decides the type of operation. Usually, the digital output signal from digital signal processor is given to digital to analog converter. The digital to analog converter gets an analog equivalent of the output digital signal. Analog, signal Analog [signal Fig, 6.1 Basic elements of a digital signal processing 6.2 D/A Converters A DAC (Digital to Analog Converter) accepts an n-bit input word by, by, b3, . by in binary and produce an analog signal Vg = Analog output proportional to it. Fig. 6.2(a) shows circuit symbol and input-output characteristics of a 4-bit DAC. There are four digital inputs, indicating 4-bit DAC. Each digital input requires an electrical signal eae 0. ihe t, a eee least Fig. 6.2 (a) DAC circuit symbol significant bit, LSB, whereas b, is the most significant bit, MSB. Fig. 6.2 (6) shows analog output voltage V, is plotted against all 16 possible digital input words. by by By ..p, = Digital inputsVors—-15 8 “4 Dashed envelope of 14 13) ‘output voltage vs. 13 digital o @ ‘onan 12 30 " £10 0 8 4 4 ge : zs 7 7 2 & 6 5 5 ‘ Output value for 4 3 1 LSB input 3 2 2 1 1 0 b—-e- opr e rer ote r or ee bo op PO Or KOO HPP OOK b—-o oo or Ke HOD oor ee a Fig. 6.2 (b) 6.2.1 Performance Parameters of DAC The various performance parameters of DAC are, Resolution Resolution is defined in two ways. + Resolution is the number of different analog output values that can be provided by a DAG. For an n-bit DAC resolution = 2" ‘+ Resolution is also defined as the ratio of a change in output voltage resulting from’a change of 1 LSB at the digital inputs. For an n-bit DAC it can be given as where, resolution = “ors m4 Yaps = Full scale output voltage ‘Ve Value in LSBs D/A and A/D Converters, VFC and FVC (dy @ From equation 1, we can say that, the resolution can be determined by the number of bits in the input binary word. For an -bit DAC resolution can be given asAnalog and Digital Electronics 6-4 D/A and A/D Converters, VFC and FVC resolution = 2" = 28 = 256 If the full scale output voltage is 10.2 V then by second definition the resolution for an B-bit DAC can be given as Mors _ 102 _ 102 ==> = Gee = 40 mV/LSB resolution = 27-1 28-4 255 Therefore, we can say that an input change of 1 LSB causes the output to change by 40mv. From the resolution, we can obtain the input-output equation for a DAC. Thus V,, = resolution x D where D = decimal value of the digital input and Vg = output voltage The resolution takes care of changes in the input. Accuracy It is a comparison of actual output voltage with expected output. It is expressed in percentage. Ideally, the accuracy of DAC should be, at worst, + , of its LSB. If the full scale output voltage is 10.2 V then for an 8-bit-DAC accuracy can be given as N, Accuracy = —oS__ -@ ny ® 102 = o55x0 7 20 mV Monotonicity A converter is said to have good monotonicity if it does not miss any step backward when stepped through its entire range by a counter. Conversion Time It is a time required for conversion of analog signal into its digital equivalent. It is also called as setting time. It depends on the response time of the switches and the output of the amplifier. Settling Time This is the time required for the output of the DAC to settle to within + 1/2 LSB of the final value for a given digital input i. zero to full scale. Stability The performance of converter changes with temperature, age and power supply variations. So all the relevant parameters such as offset, gain, linearity error and monotonicity must be specified over the full temperature and power supply ranges. These parameters represent the stability of the converter.Analog and Digital Electronics. 6-5 D/A and A/D Converters, VFC and FVC nm Example 6.1: An 8 bit DAC has an output voliage range of 0 - 2.55 V. Define its resolution in two ways. Solution : For the given DAC, n = number of bits = 8 i) resolution = 2" = 28 = 256 ie, the output voltage can have 256 different values including zero. ii) Vopg = Full scale output voltage Vers, 2.55 _ 10mV * resolution = Sm = TSB Thus an input change of 1 LSB causes the output to change by 10 mV. => Example 6.2: The digital input for a 4-bit DAC is 0110. Caleulate its final output voltage. Solution : For given DAC, n=4 Vors = 15.V A resolution = 2S. = —15_ = 1 v/isp 2-1 2t4 resolution x D Now D = decimal of (0110), = 6 Vz = 1V/LSBx6=6V ‘> Example 6.3: An 8 bit DAC has resolution of 20 mV/LSB. Find Vipq and V, if the input is (10000000), Solution: sesatution = ate \, 29 = ors. a Vors = 5:1 V D = equivalent of (10000000) = 128 V,, = resolution x D = 20 x 128 = 256 V ‘mp Example 6.4: Find out stepsize and analog output for 4-bit R-2R ladder DAC when input is 1000 and 1111. Assume Vig =+5V.Analog and Digital Electronics 6-6 D/A and A/D Converters, VFC and FVC Solution : For given DAC, = 4, Vops = +8V \ Resolution = “ors. 5 __ 1 visp eal 2.4 3 o \, = Resolution x D For D = decimal of (1000), = 8 VY = 4x8 = 2.6667 V For D = decimal of (1111), = 15 Ve = Jas a5. wm Example 6.5: A 12-bit DAC has a step size of 8 mV. Determine the full scale output voltage and percentage resolution. Also find the output voltage for the input of 010101101101? Solution : For 12-bit DAC, step size is &mV. Vors = &mVx(2! -1) = 32.76 V fon = S@Y t00 2 % Resolution = Ba 79™ 100 = 0.02442 ‘The output voltage for the input 010101101101 is = 8mVx(1389)9 = 11.112 V 6.2.2 Basic Conversion Techniques ‘There are mainly two techniques used for analog to digital conversion * Binary weighted resistor D/A converter © R/2R ladder D/A converter In these techniques, the shunt resistors are used to generate n binary weighted currents, These currents are added according to switch positions controlled by the digital input and then converted into voliage to give analog voltage equivalent to the digital input. Therefore, such digital to analog converters are called current driven DACs. Binary Weighted Resistor D/A Converter ‘The binary weighted resistor DAC uses an op-amp to sum n binary weighted currents derived from a reference voltage Vp via current scaling resistors 2R, 4R, 8R, ..., 2" R, as shown in the Fig. 6.3. As shown in the Fig. 6.3, switch positions are controlled by the digital inputs, When digital input is logic 1, it connects the corresponding resistance to the reference voltage Vp; ‘otherwise it leaves resistor open. Therefore,Analog and Digital Electronics 6-7 D/A and A/D Converters, VFC and FVC by b2 Bs bn For ON-switch, I = —® and For OFF-switch, I= 0 Here, operational amplifier is used as a summing amplifier. Due to high input impedance of op-amp, summing current will flow through Rj. Hence the total current through R; can be given as Ip = tht teeth, The output voltage is the voltage across Ry and it is given as Vo = = 0.5625 Vp = 2.8125 VAnalog and Digital Electronics 6-10 DIA and A/D Converters, VFC and FVG The inverting R/2R ladder DAC works on the principle of summing currents and it is also said to operate in the current mode, An important advantage of the current mode is that all ladder node voltages remain constant with changing input codes, thus avoiding any shutdown effects by stray capacitances. R/2R Ladder D/A Converter In this type, reference voltage is applied to one of the switch positions, and other switch position is connected to ground, as shawn in the Fig. 6.6. Fig. 6.6 R/2R ladder D/A converter Let us consider 3-bit R/2R ladder DAC with binary input 001, as shown in the Fig. 6.7. Fig. 6.7 3-bit RI2R ladder DACAnalog and Digital Electronics 6-11 D/A and A/D Converters, VFG and FVG Reducing above network to the left by Thevenin's theorem we get, Fig, 6.8 (b) R ‘ env be s+ Fig. 6.8 (c) Therefore, the output voltage is Vz/8 which is equivalent to binary input O01. For binary input 100 the network can be reduced as follows : Fig. 6.9 (a)Analog and Digital Electronics D/A and A/D Converters, VFC and FVC Vpl2 = Va Fig. 6.9 (b) Therefore, the output voltage is Vp/2, which is equivalent to binary input 100. In general, the expression for V, can be obtained as, Let Tye: = Output current R, = feedback resistance of op-amp * Vo = ~ Tout Rp Now Tye = current resolution x D * V, = ~ (current resolution x D) Ry * Vz = ~ (current resolution x R)) x D we (1) The coefficient of D is the voltage resolution and can be called as simple resolution. V, = ~ resolution x D ae (12) In terms of actual circuit elements, output can be written as, Vay t Vy = (Ct eh fo (13) resolution = w+» (14) while the resolution fo R/2R ladder type DAC with voltage output is, . 1. VR resolution = (rt em wne(15) imp Example 6.6 : Suggest the values of resistors and reference voltage if resolution required is 0.5 V for 4 bit R/2R ladder type DAC. Vr Solution : resolution = {xR Re 7 R Let Va = 10 V, n= 4 and resolution = 05 110 05 = wR Ry R “ eer = 15 RyAnalog and Digital Electronics 6-13 D/A and A/D Converters, VFC and. FVC Choose R, = 10k ” R=L5Q Advantages of RI2R ladder DACs : 1, Easier to build accurately as only two precision metal film resistors are required 2. Number of bits can be expanded by adding more sections of same R/2R values. 3. In inverted R/2R ladder DAC, node voltages remain. constant with changing input binary words. This avoids any slowdown effects by stray capacitances. 6.2.3 Sources of Errors in DAC There are mainly three errors in DACs : Linearity, offset and gain errors. Linearity Error The error is defined as wl —* Ideat the amount by which the set actual output differs from aot Non linearity the ideal __ straight-line output. ve Fig. 6.10 shows the linearity error in the transfer characteristics of DAC. It is mainly due to the errors in Fig. 6.10 Linearity error in transfer characteristics of the current source resistor DAG values. 26-- 184 0 Offset Error The offset error is Actual —2///o— Ideal defined as the nonzero level of the output voltage when all inputs are zero. It adds a constant value to all output values, as shown in Fig. 6.11. It is due to the presence of offset voltage in op-amp and leakage Fig. 6.11 Offset error in transfer characteristics of DAC currents in the current switches.Analog and Digital Electronics 6-14 D/A and AID Converters, VFC and FVC Gain Error 78 + ef Gain Emor Fig. 6.12 Gain error in tansfer characteristics of 6.2.4 IC 1408 D/A Converter Devices Fig. 6.13 (a) Pin diagram It is defined as the difference between the calculated gain of the current to voltage converter and the actual gain achieved. It is due to the errors in the feedback resistor on the current to voltage converter op-amp. Fig. 6.12 shows the gain error in transfer characteristics of DAC. The 1408 is an 8 bit R/2R ladder type D/A converter compatible with TTL and CMOS logic. It is designed to use where the output current is linear product of an eight bit digital word. Fig. 6.13 (@) shows the pin diagram and block diagram for Ic 1408 DAC. The IC 1408 consists of a reference current amplifier, an R/2R ladder and eight high speed current switches. It has eight input data lines A, (MSB) through Ag (LSB) which control the positions of current switches. It requires 2.mA reference current for full scale input and two power supplies Voc= +5 Vand Veg = - 15 V (Veg can range from - 5 V to - 15 V). ‘The voltage Vrei and resistor Ry, determines the total reference current source and Rys is generally equal to R,, to match the input impedance of the reference current amplifier.Analog and Digital Electronics 6-45 DIA and A/D Converters, VFC and FVC MsB LsB ‘Compensation E EL NPN Current source pair Fig. 6.13 (b) Block diagram Fig, 6.14 shows a typical circuit for IC 1408. The output current I, can be given as vi A A, A. A, = Met (At +As Ar, As Ry ( 2+ 64” 128 2] 8) Note ; Input A; through Ag can be either 0 or 1. Therefore, for typical circuit full scale current can be given as, _ 5 flit l= zaK(2*et 8" 16 _ 2mAx 255 “36 = 1992 mAAnalog and Digital Electronics D/A and A/D Converters, VFC and FVC B-bit digit input Fig. 6.14 Typical circuit for IG 1408 It shows that the full scale output current is always 1 LSB less than the reference current source of 2 mA. This output current is converted into voltage by I to V converter. The output voltage for full scale input can be given as Vo = 1.992% 2.5K = 4.98 V Note : The arrow on the pin 4 shows the output current direction. It is inward. This means that IC 1408 sinks current. At (0000 0000), binary input it sinks zero current and at (11111111), binary input it sinks 1992 mA. The circuit shown in the Fig. 6.14 gives output in the unipolar range. When digital input is 00H, the output voltage is 0V and when digital input is FFH (11111111), the output voltage is + 5 V. This circuit can be modified to give bipolar output. Fig. 6.15 shows the circuit for giving output in the bipolar range. Here, resistor Rg(S K) is connected between Vyer and the output terminal of IC 1408. This gives a constant current source of 1 mA. The circuit operation can be observed for three conditions : Condition 1 : For binary input (00H) When binary input is 00H, the output current I, at pin 4 is zero. Due to this current flowing through Rg (1 mA) flows through Ry giving Vo = - 5 V.Bbit digitat input EE Fig. 6.15 Interfacing DAC in the bipolar range Condition 2 : For binary input 60H. When binary input is 80H, the output current I, at pin 4 is 1 mA. By applying KCL at node A we get, -Igtly+lp = 0 Substituting values of Ig and I, we get, (1 mA) + (1 mA) + I, " ° = 0 and therefore the output voltage is zero. Condition 3 ; For binary input FFH When binary input is FFH, the output current I, at pin 4 is 2 mA. By applying KCL at node A we get, -Iy +I #1, substituting values of Ig and |, we get, - (mA) + @QmA) +], = 0 ly = -1mA Therefore, the output voltage is + 5 V. In this way, circuit shown in the Fig. 6.15 gives output in the bipolar range. " °6-18 D/A and AID Converters, VFC and FVC and Digital Electronics Important Electrical Characteristics for IG 1408 :2mA 2 +5 Veg and — © Reference current Supply voltage © Setting time 3300 ns © Full scale output current: 1,992 mA © Accuracy 0.19 % 6.3 AID Converters Analog Input ane be Dy be Dy Fig. 6.16 Symbol for 4 bit ADG 6.3.1 Performance Parameters of ADC 15 V Veg The A/D conversion is a quantizing process whereby an analog signal is converted into equivalent binary word. Thus the A/D converter is exactly opposite function that of the D/A converter. Fig. 6.16 shows symbol for A/D converter. ‘The Fig. 6.17 shows the digital output of an ideal 3 bit ADC plotted against the analog input voltage. 718 Digital output Analog input Fig. 6.17 Analog input Vs Digital output Ideal Transition Ideally quantized analog inputAnalog and Digital Electronics 6-19 D/A and A/D Converters, VFC and FVG Let us define the performance parameters of ADC, referring to the Fig. 6.17, which shows the output-input characteristics of ADC, Resolution Fig. 6.17 shows eight (2°) discrete output states from 000, to 111,, each step being iv apart. Therefore, we can say that expression of ADC resolution is the same as for the DAC and is repeated here : resolution = 2" 17 Resolution is also defined as the ratio of a change in value of input voltage, V;, needed to change the digital output by 1 LSB. If the full scale input voltage required to cause a digital output of all 1's is Vipg, then resolution can be given as resolution = —Y#S_ ves (18) 2-1 Quantization Error Fig. 6.17 shows that the binary output is 011 for all values of ¥; between 4 and UV. There is an unavoidable uncertainty about the exact value of V, when the output is O11. This uncertainity is specified as quantization error. Its value is + 3 LSB. It is given as, s+ (19) Increasing the number of bits results in a finer resolution and a smaller quantization error. Conversion Time It is an important parameter for ADC. It is defined as the total time required to convert an analog signal into its digital output. It depends on the conversion technique used and the propagation delay of circuit components. tmp Example 6.7 : An 8-bit ADC outputs all 1’s when V, = 5.1 V. Find its a) Resolution and b) Digital output when V; = 1.28 V Solution : a) From equation (20) we have, resolution = 2° = 256 and from equation (18) we have, resolution = 21% = 29 mv/LsB 28-1 Therefore, we can say that to change output by 1 LSB we have to change input by 20 mV.Analog and Digital Electronics 6-20 DIA and AID Gonverters, VFG and FVG b) For 1.28 V analog input, digital output can be calculated as, 128V D = ——"*__ = 64 LSBs 20 mV / LSB The binary equivalent of 64 is 0100 00005 iam Example 6.8 : Calculate the quantizing error for 12-bit ADC with full scale input voltage 4.095 V. Solution ; From equation (19) we get 4095 Q, = — _ EB (22 =1x2 6.3.2 Basic Conversion Techniques Analog to digital converter are classified into two general groups based on the conversion techniques. One technique involves comparing a given analog signal with the internally generated reference voltages. This group includes successive approximation, flash, delta modulated (DM), adaptive delta modulated and flash type converters. The another technique involves changing an analog signal into time or frequency and comparing these new parameters against known values. This group includes integrator converters and voltage-to-frequency converters. In this chapter we are going to discuss following types of ADCs using various conversion techniques : 1. Single ramp or single slope 2. Dual slope 3. Successive approximation 4. Flash 5. Delta modulation 6. Adaptive delta modulation Single Slope ADC It consists of a ramp generator and BCD or binary counters. The Fig. 6.18 shows the single slope ADC. Ciéck o Fig. 6.18 Single slope ADCAnalog and Digital Electronics 6-21 D/A and A/D Converters, VFC and FVC At the start, the reset signal is provided to the ramp generator and the counters. Thus counters are resetted to 0's. The analog input voltage Vin is applied tc the positive terminal of the comparator. As this is more positive than the negative input, the comparator output goes high. The output of ramp generator is applied to the negative terminal of the comparator. The high output of the comparator enables the AND gate which allows clock to reach to the counters and also this high output starts the ramp. The ramp voltage goes positive until it exceeds the input voltage. When it exceeds Vig, comparator output goes low. This disables AND gate which inturn stops the clock to the counters. The control circuitry provides the latch signal which is used to latch the counter data. The reset signal resets the counters to 0’s and also resets the ramp generator. The latched data is then displayed using decoder and a display device. Let us consider the practical example to understand the working. Assume that the clock frequency is 1 MHz. There are four BCD counters and the input Vin is 2.000 V. Now let ramp has a slope of 1V/ms as shown in the Fig. 6.19. As the input is 2.000 V, the ramp will take 2 ms to reach to 2 V and to volts v stop the clock to the counters. KoA Now how many pulses will reach to the ms counters during 2 ms ? It can be calculated ms from the frequency of the clock. The number of pulses reaching to the counter in 2 ms is Fig. 6.19 = 2000. The comparator output (7 IMAa) going high will strobe. The latches and send the count to the displays. Inserting a decimal point at the proper point in the seven segment display gives a reading of 2.000. But we want binary output. In such case instead of BCD counters, binary counters must be used, where output will be straight binary coded. The main limitations of this circuit are, i) Its resolution is less. Hence for applications which require resolution of 9 part in 20,000 or more, this ADC is not stable. ii) Variations in ramp generator due to time, temperature or input voltage sensitivity also cause a lot of problems. Dual Slope ADG Dual slope conversion is an indirect method for A/D conversion where an. analog voltage and a reference voltage are converted into time periods by an integrator, and then measured by a counter. The speed of this cunversion is slow but the accuracy is high. Fig. 6.20 shows a typical dual slope converter circuit. It consists of integrator (ramp generator), comparator, binary counter, output latch and reference voltage. The ramp generator input is switched between the analog input voltage V, and a negative reference voltage, Vace. The analog switch is controlled by the MSB of the counter. When the MSBAnalog and Digital Electronics 6-22 DIA and A/D Converters, VFC and FVG is a logic 0, the voltage being measured is connected to the ramp generator input. When MSB is logic 1, the negative reference voltage is connected to the ramp generator. input Veer Digital output Fig. 6.20 Dual slope A/D converter Fig. 6.21 Integrator output voltage At time t = 0, analog switch S is connected to the analog input voltage Vj, so that the analog input voltage integration begins. The output voltage of the integrator can be given sve (20)Analog and Digital Electronics 6-23 D/A and A/D Converters, VFC and FVC where R, C, is the integrator time constant and Vj is assumed constant over the integration time period. At the end of 2N clock periods MSB of the counter goes high. At a result the output of the flip-flop goes high, which causes analog switch S to be switched from Vj to -Vg. At this very same time the binary counter which has gone through its entire count sequence is reset. The negative input voltage (-Vp) connected to the input of integrator causes the integrator output to ramp positive. When integrator output reaches zero, the comparator ‘output voltage goes low, which disables the clock AND gate. This stops the clock pulses teaching the counter, so that the counter will be stopped at a count corresponding to the number of clock pulses in time ty. The integrator output ramp down to a voltage V and get back upto 0. Therefore, the charge voltage is equal to discharge voltage and we can write, Mti _ Mete Re RG Vity = Vp ty a ty was (21) YR The above equation shows that t, is directly proportional only to the V;, since Vp and ty are constants. The binary digital output of the counter gives corresponding digital value for time period t and hence it is also directly proportional to input signal Vj. The actual conversion of analog voltage V;, into a digital count occurs during tj. The control circuit connects the clock to the counter at the beginning of t;. The clock is disconnected at the end of t,. Thus the counter contents is digital output. Hence we can write, digital output (Sant } 2 (22) second But from (21) we can write, counts \, (Vj (Sema) (sf) 3) The counter output can then be connected to an appropriate digital display. The advantages of dual slope ADC are 1. It is highly accurate. 2. Its cost is low. 3. It is immune to temperature caused variations in R, and C,. ‘The only disadvantage of this ADC is its speed which is low. digital output tus Example 6.9 : For a particular dual slope ADC, t, is 83.33 ms and the reference voltage is 100 mV. Calculate ty if i) V; is 100 mV and ii) 200 mV.Analog and Digital Electronics 6-24 D/A and A/D Converters, VFC and FVC Solution : We know that, =“ vet = (300) 339 = 83.33 ms = 200 mV be (ian )o339 = 166.6 ms ii) ump Example 6.10 : Fini! the digital output of an ADC having 1, as 83.33 ms and Vp as 100 mV for an input voltage of + 100 mV. The clock frequency is 12 kHz. Solution : The digital output is given as, voi counts), (¥ digital output = (3). () Now Clock frequency = 12 kHz ie. = 12000 US second . isi _ 10 3 n igital output = 12000 x 83.33 (755 x 10” = 1000 counts. Successive Approximation ADC In this technique, the basic idea is to adjust the DAC’s input code such that its output is within + }4 LSB of the analog input V; to be A/D converted. The code that achieves this represents the desired ADC output The successive approximation method uses very efficient code searching strategy called binary search. It completes searching process for n-bit conversion in just n clock periods. Fig. 6.22 shows the block diagram of successive approximation A/D converter. It consists of a DAC, a comparator, and a successive approximation register (SAR). The external clock input sets the internal timing parameters. The control signal start of conversion (SOC) initiates an A/D conversion process and end of conversion signal is activated when the conversion is completed.Analog and Digital Electronics 6-25 DIA and A/D Converters, VFC and FVC Start of End of ‘conversion (SOC) conversion (EOC) Vio Analog input Output of DAC Fig, 6.22 Block diagram of successive approximation AID converter Operation ; The searching code process in successive approximation method is similar to weighing an unknown material with a balance scale and a set of standard weights. Let us assume that we have 1 kg, 2 kg and 4 kg weights (SAR) plus a balance scale (comparator and DAC). Now we will see the successive approximation analogy for 3-bit ADC. Refer Fig. 6.22 and 6.23. The analog, voltage Vin is applied at one input of comparator. On receiving start of conversion signal (SOC) successive approximation register sets 3-bit binary code 100, (b, = 1) as an input of DAC. This is similar process of placing the unknown weight on one platform of the balance and 4 kg weight on the other. The DAC converts the digital word 100 and applies its equivalent analog output at the second input of the comparator. The comparator then compares two voltages just like comparing unknown weight with 4 kg weight with the help of balance scale. If the input voltage is greater than the analog output of DAC, successive approximation register keeps b = 1 and makes b, = 1 (addition of 2 kg weight to have total 6 kg weight) otherwise it resets by = O and makes b; = 1 (replacing 2 kg weight), The same process is repeated for by and bg. The status of bg, b, and b, bits gives the digital equivalent of the analog input. Fig. 6.23 illustrates the process we have just discussed. The dark lines in the Fig. 6.23 shows setting and resetting actions of bits for input voltage 5.2 V, on the basis of comparison. It can be seen from the Fig. 6.23 that one clock pulse is required for the successive approximation regsiter to compare each bit. However an additional clock pulse is usually required to reset the register prior to performing a conversion.Analog and Digital Electronics 6-26 DIA and AID Converters, VFC and FVC: Start of conversion (SOC) Start End CL Cock Le LL Compare Compare Compare MsB by by baby by om 000 Fig. 6.23 Illustration of conversion process The time for one analog to digital conversion must depend on both the clock’s period T and number of bits n. It is given as, To =Tm+t where Te = conversion time T = clock period number of bits (24) " WAnalog and Digital Electronics 6-27 D/A and A/D Converters, VFC and FVC im Example 6.11: An & bit successive approximation ADC is driven by a 1 MHz clock. Find its conversion time. Solution : f = 1 MHz 1 1 Tecies = 1 psec Fteoe | n=8 ” To = Tin+ 1) =1@+ 1) =9 psee. Flash ADC or Parallel Comparator ADC When system designs call for the highest speed available, flash-type A/D converters (ADCs) are likely to be the right choice. They get their names from their ability to do the conversion very rapidly. Flash A/D converters, also known as a simultaneous or parallel comparator ADC, because the fast conversion speed is accomplished by providing 2° - 1 Fig. 6.24 3-bit flash converterAnalog and Digital Electronics 6-28 DIA and A/D Converters, VFC and FVC comparators and simultaneously comparing the input signal with unique reference levels spaced 1 LSB apart. Fig. 6.24 shows 3-bit flash A/D converter. For this ADC, seven (2 - 1) comparators are required. As shown in the Fig. 6.24, one input of each comparator is connected to the input signal and other input to the reference voltage level generated by the reference voltage divider, The reference voltage (Vggr ) is equal to the full scale input signal voltage. ‘The manner in which the flash A/D converter performs a quantization is relatively simple. The comparators give output “1" or “0” state depending on whether the input signal is above or below the reference level at that instant. Those comparators referred above the input signal, remain turned-off, representing a “O" state. The comparators at or below the input signal conversely become a “i” state. The code resulting from this comparator is converted to a binary code by the encoder. The number of comparators required for n bit resolution is, number of comparators = 2" —1 25) As seen earlier the quantization error is ++ } LSB. Thus for an ADC, the maximum frequency for a sine wave Vin to be digitised within an accuracy of + 5 LSB is, 1 “Sa (26) where fnax = maximum input frequency Tg = conversion time n = number of bits ‘ump Example 6.12: For a particular 8-bit ADC, the conversion time is 9 ys. Find the maxinnum frequency of an input sine wave that can be digitized. Solution : The maximum frequency is given by, £4, = —b— «= __1__ mex 2x(Te)2" — Qxx 9x10 x 28 ~ 69.07 Hz Comparison between Flash, Dual Slope and Successive Approximation Techniques The comparison of ADCs is given in the tabular form as below : Parameter Flash Successive Dual slope approximation Speed Fastest Fast Slow Accuracy Less Medium More Resolution Upto 2° Upto 218 2'8 or even moreAnalog and Digital Electronics 6-29 D/A and A/D Converters, VFC and FVC AID Converter ICs ADC 0803 Family Input hold Depend on number of | It is maximum, hence time ‘bits. It is more than flash | sample and hold circuit AND converter is required Cost Medium Less Applications | High speed fiber optic | The successive ‘These are used when cormmunicatian, Digital | approximation A/D high accuracy and storage oscilloscope, converter has the resolution is required and Imaging and many more | disadvantage of requiring | speed is not the where high speed AID | DJA converter, but it has | important criteria. conversion is required | the advantage of high speed with excellent resolution. Hence these ‘are most popular and used in data acquisition systems 1c |Resol-|Gon- | i¢ [Resol|Gonvers+ | ¢ _ |Resol |Conversi- tion |version -ution Jon rate -ution |on rate rate ICs japeng0Ko| 6 [soma [Abciios | 8 | whe [adow; | i | 25He japeoooso| 6 |rsmiz [ances | 10 | evox |ri09 12_|_ soni frwt070 fs mitz [ADonioa | 12 | sooxte |aoetzco | 12 | zehz foci + ps ADCTE urrsso0 2] zene. The ADC 0803 and ADC 0805 are CMOS 8-bit successive approximation analog to digital converters, These devices are design to operate from common microprocessor control buses, with tri-state output latches driving the data bus. Fig. 6.25 shows the pin diagram of ADC 0803 and ADC 0805. Apc 0803) 0805, Veo ctx our [5 peo 5 ost [5 ps2 5 os ops Des 0B6 [5 087 18 7 16 15 14 9 12 DATA ‘OUTPUTS Fig. 6.25 Pin diagram of ADCOB03/0805 IN+ and IN- inputs allow application of differential input voltage which has high common mode rejection and eliminates offset due to the zero input analog voltage value. The devices can operate with an external clock signal or, the on chip clock generator can be used independently by adding an external resistor and capacitor to set the time period.Analog and Digital Electronics 6-30 DJA and AID Converters, VFC and FVC The main features of these family are : Features ‘© Bbit successive approximation ADC © Conversion time 100 us © Access time 135 ns It has an on-chip clock generator © It does not require any zero adjustment. © It operates on single 5V power supply © Output meet TTL voltage level specifications. ‘Operation When the WR input goes low, the internal successive approximation register (SAR) is reset. As long as both CS and WR remain low, the analog to digital converter will remain in its reset state. One to eight clock periods after CS or WR makes a low-to-high transition, conversion starts. The INTR signal is held high during conversion process. After conversion, INTR goes low which is used as end of conversion signal. By making CS and RD signals low, an output can be read through DBO to DB7 data signals. ADC 0808/0809 Family The ADC 0808 and ADC 0809 are monolithic CMOS devices with an channel multiplexer. These devices are also designed to operate from common microprocessor control buses, with tri-state output latches driving the data bus. The main features of these devices are: Features © &bit successive approximation ADC * 8channel multiplexer with address logic © Conversion time 100 jis © It eliminates the need for external zero and full-scale adjustments «Easy to interface to all microprocessors © It operates on single 5V power supply © Output meet TIL voltage level specifications Fig. 6.26 shows pin diagram of 0808/0809 ADC ADC 0808/0809 has eight input channels, so to select desired input channel, it is necessary to send 3-bit address on A, B and C inputs, The address of the desired channel is senti to the multiplexer address inputs through port pins. After at least 50 ns, this address must be latched. This can be achieved by sending ALE signal. After another 2.5 1s, the start of conversion (SOC) signal must be sent high and then low to start the conversion Process, To indicate end of conversion ADC 0808/0809 activates EOC signal. The sor system can read converted digital word through data bus by enabling the output enable signal after EOC is activated. This is illustrated in Fig. 6.27.Analog and Digital Electronics 6-31 DIA and A/D Converters, VFC and FVC ° ? | analog sea ‘ 1p a inputs 6 A 7 B } Address soc c EOC ALE DB3 DB7 OUTPUT CONTROL DBS cu C] DBs Vee DB4 reF+(] 12 DBO GND REF Det DB2 0c. Fig. 6.27 Timing waveforms for ADC 0808 Ie 7109 The ICL 7109 is a high performance, low power integrating (Dual slope) A/D converter designed to easily interface with microprocessor.Analog and Digital Electronics 6-32 D/A and A/D Converters, VFC and FVC Features IC 7109 is a 12-bit dual slope A/D converter. It has polarity and over range bits. It has byte organized TTL compatible three-state outputs and UART handshake mode for simple parallel or serial interfacing to microprocessor systems. It has RUN/HOLD input-and STATUS output, which can be used to monitor and control conversion timing. ery - 5. It has true differential input and differential reference 6. It has low noise-typically 15 WVp p+ 7. It has very low input current - IpA 8. It operates at 30 conversions per second. 9. All inputs are fully protected against static discharge. Pin Configuration and Test Circuit The Fig. 6.28 shows typical circuit and pin configuration for 7109. eno —{i] cn Z| STATUS POL HIGH Aj0R ORDER Biz BYTE é len © Input high a Z Input ow a 3 IcL 7109. RENIN® *RINT=20 ka -0F 200K REN/ OLD [26} REFOSC OUT [25 ‘osc set [24}- GND ose OUT ae 3.5785 MHz OSC IN [za] Fig. 6.28 Pin diagram of ICL 7109Analog and Digital Electronics 6-33 DIA and A/D Converters, VFC and FVC wom Example 6.13 : A 6-bit DAC has an input of 100101 and a 10 V reference. Find ; i) Output voltage produced. ii) Conversion resolution. Solution : Ry R2R3 R4 RS N4 S, 8, s] Se] Ss] Sa] Sol =| =) Sl =) =! evss) Vp Fig. 6.29 = Ss, S, s. «asi “t The voltage at node N ~ 1 i.e. 5 is V’ = Lp. when only MSB is applied In general output voltage Vo is Vi= (enertgewerttsairte J2t¥ In our case 1 L Vy e (Iro+o+g +043 |v) A 10 * Vy = (1.15625) "Oca = 3.85416 x A volts where A= 1+ & gain of non-inverting amplifier ‘1 Resolution = 2x12 4 = 0.104 volts = gpg Ana imp Example 6.14: The sample and hold (S/H) circuit shown in Fig. 6.30 was used in a interface for temperature control. Show that the acquisition time for a step input of 10 V is less than 100 41s. The op-amp 741 can supply a maximum of 25 mA. and the slew rate can be neglected. The ON resistance of the FET is 30.Q. Assume an accuracy of 0.5 % of final value.Analog and Digital Electronics 6-34 DIA and A/D Converters, VFC and FVC Gate Fig. 6.30 Solution : Given : Rp oy(On resistance of FET) = 30.9, The time constant, t = (R, + Rp ox) © where R, - output resistance of op-amp which is 75 Q for op-amp74l. = (5 +30) ‘The capacitor C ean be given as C = Cy, (op-amp) + Coy (FET) = 14 pF + 10 nF = 10nF ¥ = 105% 10 = 1050 ns For 0.5% tolerance, the hold capacitor voltage can be given as Vc = Step input voltage - 0.5 % of Step input voltage = 10-005 = 995 V Vo = V(b-ert/RCy 9.95 = 10 (1 e°t/(50x10"%) t = 556s ‘Therefore, time required to charge the capacitor (5.56 lis) upto 9.95 V which is very much less than 100 pis. imap Example 6.15: A dual slope uses a 8-bit counter and a 3 MHz clock rate. The maximum input voltage is +10 V. The maximum integrator output voltage should be ~ 8 V, when the counter cycled through 2's counts, The capacitor used in the integrator is 0.1 UF. Find the value of 'R! of the integrator. How the RC-product limits the speed of ADC ? Solution :Analog and Digital Electronics 6-35 DIA and AUD Converters, VFC and FVC Vy = -8 = ——~__- (85.33) x10 Rx0.1x10% » 853.3 O.1R R = 1066625. Conversion time depends on RC time constant. The counter count is proportional to Vj, and is independent of RC. = Min ne ob? ii) If V, = 4.129 V and Vp = 8 V in the part (i). Obtain the digital count ‘N’ and also obtain the digital output is 2's complement. ~ Mion 1s ye _ 4.129 == 132 = 10000100 In 2's complerent the digital output will be = 01111100, 28 6.4 Voltage to Frequency Converter (VFC) ‘A voltage to frequency converter (VFC) produces a pulse train whose frequency is linearly proportional to an analog input voltage, four = ky Vi we (l) In other words, it converts analog signals to digital form. The primary reason for this type of conversion is that a pulse train can be transmitted and decoded much more accurately than an analog signal, especially if the transmission path is long and noisy. 6.4.1 Typleal Specifications of VFCs * wide dynamic range (more than four decades) ability to operate to relatively high frequencies (hundreds of kHz, or higher) © low linearity error (less than 0.1 percent deviation from the straight line going from zero to full scale.) © high scale-factor accuracy © stability with temperature and supply voltage.Analog and Digital Electronics 6-36 D/A and A/D Converters, VFC and FVC: 6.4.2 Types of VFC'S According to the method of conversion there are two types of VECs : * Wide sweep multivibrators and * Charge-balancing VFCs 6.4.2.1 Wide-Sweep Multivibrator VFCs Wide sweep multivibrator circuits are nothing but the voltage controlled astable multivibrators designed with VFC performance specifications in mind. Such circuits. are temperature stabilized. ADS537 is a popular VEC in this type from analog devices. Fig. 6.31 shows block diagram and basic connections for AD537. Fig. 6.31 As shown in the block diagram conversion takes place in two steps ; Initially, input voltage is converted to the current drive, and then current controlled oscillator (CCO) produces pulses whose frequency is linearly proportional to the input current. The input voltage is converted to the current drive with the help of op-amp and BJT combination. The op-amp provides base current to ensure Vy= Vp. Thus I = V; /R. The CCO parameter is such that, I fou = STOW ~@ Substituting value of I we get,Analog and Digital Electronics 6-37 DIA and A/D Converters, VFC and FVG t ¥ ‘out ~ RO IOV --@) For Ad537, this linear relationship. remains accurate over a dynamic range of atleast four decades, upto a full-scale current of ImA and a full-scale frequency of 100 kHz. Let us assume, C = 1 nF, R= 10 k and V¢c= 15 V. Now, variation of V; from 1 mV to 10 V gives current and hence frequemcy variations as follows. ‘Current Variation : For 1 mV Inv. T= Ggpge = OMA 10V For 10 V, les Tom = 1™4 Frequency variations : For 0.1 1A 01 A fout = Tapciov = 10 He 0.1 mA For 1 mA, fout = Tageigy = 100 KHz ‘The Rog (20 K pot) is connected to minimize the V-I conversion error at the low end of the range. It does this by making input offset error of op-amp zero. The on chip precision voltage reference stabilizes the CCO scale factor. The voltage references are also made available with the help of terminals Vp (pin 7) and Vy (pin 6). Vp is stable 1.00 V reference voltage and Vy is a voltage linearly proportional to absolute temperature T. It is given by Vy = ImV/°KxT. 6.4.2.2 Charge Balancing VFCs In charge balancing technique, a capacitor is supplied with a continuous charge at a rate linearly proportional to the input signal. Then capacitor is discharged and simultaneously discrete charge pulse is generated with the help of one shot (monostable multivibrator). Therefore, for each charge-discharge cycle one pulse is generated. The repetition rate of these train of pulses is directly proportional to the input signal since charge rate is linearly proportional to the input signal. Fig. 631 shows block diagram of popular VEC32 monolithic VFC as a charge balancing VEC. ‘As shown in the Fig. 6.31 (a) op-amp A, converts V; to current I = V,/R, which flows into a summing node of Ay (inverting input of Ay). The value of R is chosen such that I is always less than 1 mA. To understand circuit operation, let us consider switch SW is open.Analog and Digital Electronics 6-38 D/A and A/D Converters, VFC and FVC ee Fig. 6.32 (a) Block diagram of VFC32 With SW open, current I flows into capacitor C, and causes the output of op-amp Ay (Vg) to ramp downward, as shown in the Fig. 6.32 (b). Vor —y¥— ss — Fig. 6.32 (b)Analog and Digital Electronics 6-39 D/A and A/D Converters, VFC and FVC As Vo1 reaches OV, comparator CMPI fires and triggers a precision one-shot, which closes SW and turns on transistor Q, for a time interval Ty; set by C. The one-shot utilizes an intemal threshold of 4.5 V and a charging current of ImA. This gives 75V Ty = kc eal) As soon as, switch is closed, a resultant current of magnitude (1mA - I) starts flowing ‘out of summing node of A;. This causes output voltage of Ay (Voi) to ramp upward by an amount such that 4 Vo, = [mA ~ 1) Ty ]/ C}. After the timing interval of one shot ie. after time Tyg. SW is opened and Vg; resumes ramping downward at a rate again set by L The output voltage of A; (Vo}) takes time interval Ty to reach OV such that AVo1 = 1 T/C). Now relating Ty; and T,, with above equations we get (1 mA -) Ty = TT, 8) © ImATy-ITy = IT, Dividing equation by I we get, Tet = Th ImA T, Ty+T = 4 ~-(6) 1 We know that, faye = a ol) . =i. we * fot = TmaTy “RamaT) T= MAR - i ep, = 25 * ROK TSV “Ta Tima © 6) The above equation indicates that f,. is linearly proportional to Vj, as desired. ‘The percentage duty cycle is given as Ty oT 0) Substituting value of Ty + Ty, we get, = Tw =i 4% = Raat Ty" = AIO AO) From equation 10 we can notice that duty cycle is also proportional to the input signal 7