WLSLEAQs 1, What is metastability? When setup or hold window is violated in an flip flop then signal attains a unpredictable value or state known as metastabilty. 2, What is MTBF? What it signifies? © MTBF-Mean Time Before Failure * Average time to next failure 3. How chance of metastable state failure can be reduced? * Lowering clock frequency * Lowering data speed * Using faster flip flop 4. What are the advantages of using synchronous reset ? * No matastability problem with synchronous reset (provided recovery and removal time for reset is taken care). * Simulation of synchronous reset is easy. 5. What are the disadvantages of using synchronous reset ? * Synchronous reset is slow. * Implementation of synchronous reset requires more number of gates compared to asynchronous reset design, + Anaztive clock is essential for a synchronous reset design. Hence you can expect more power consumption. 6. What are the advantages of using asynchronous reset 7 * Implementation of asynchronous reset requires less number of gates compared to synchronous reset design. * Asynchronous reset is fast. * Clocking scheme is not necessary for an asynchronous design. Hence design consumes less power. Asynchronous design style is also one of the latest design options to achieve low power. Design community is scrathing their head over asynchronous design possibilities. 7. What are the disadvantages of using asynchronous reset ? ‘+ Metastability problems are main concerns of asynchronous reset scheme (design). * Static timing analysis and DFT becomes difficult due to asynchronous reset.8, What are the 3 fundamental operating conditions that determine the delay characteristics of gate? How operating conditions affect gate delay? * Process * Voltage © Temperature 9. Is verilog/VHDL is a concurrent or sequential language? * Verilog and VHDL both are concurrent languages * Any hardware descriptive language is concurrent in nature 10. Ina system with insufficient hold time, will slowing down the clock frequency help? © No. * Making data path slower can help hold time but it may result in setup violation 11. In a system with insufficient setup time, will slowing down the clock frequency help? * Yes, + Making data path faster can also help setup time but it may result in hold violation. Physical Design Objective Type of Questions and Answers * 1) Chip utilization depends on _. a. Only on standard cells b. Standard cells and macros c. Only on macros d. Standard cells macros and IO pads + 2)In Soft blockages __cells are placed. a. Only sequential cells b. No cells c. Only Buffers and Inverters d. Any cells, * 3) Why we have to remove scan chains before placement? a, Because scan chains are group of flip flop b. It does not have timing critical path c. Its series of fp lop connected in FIFO d. None + 4) Delay between shortest path and longest pat! the clock is called 8. Use skew b, Local skew g Global shaw d, Slack * 5) Cross talk can be avoided by a. Decreasing the spacing between the metal layers b. Shielding the nets c. Using lower metal layers d. Using long nets+ 6)Prerouting means routing of 2, Clock nets b. Signal nets ¢, 10 nets d. PG nets + 7)Which of the following metal layer has Maximum resistance? Motel. Maz. Meta Metal + 8) What is the goal of CTS? 8 Minimum IR Drop b, Minimum EM g Minimum Skew d, Minimum Slack + 9) Usually Hold is fixed 2, Before Placement b. After Placement c. Before CTS d,After CTS N better timing ___cells are placed in the critical path. * 10) To achie\ 2. HVT LVT c. RVT¢. SVT * 41) Leakage power is inversely proportional to a. Frequency b, Load Capacitance c, Supply voltage h Threshold Voltage + 12)Filler cells are added __. a. Before Placement of std cells b. After Placement of Sid Cells c. Before Floor planning d, Before Detail Routing * 13) Search and Repair is used for 4. Reducing i Drop Racing DR, Redtong EM vsatins dl, None * 14) Maximum current density of a metal is available in __. 4b bv qd, sd + 15)More IR drop is due to__. a. Increase in metal width b. Increase in metal length c. Decrease in metal length d. Lot of metal layers © 16) The mi 1um height and width a cell can occupy in the design is called as__. K Unit Tile cell b. Multiheighten cell c. LVT cell d. HVT cell * 17) CRPR stands for__.a, Cell Convergence Pessimism Removal b, Cell Convergence Preset Removal ¢. Clock Convergence Pessimism Removal d. Clock Convergence Preset Removal * 18) In OCV timing check, for setup time, _. 2, Max delay is used for launch path and Min delay for capture path b. Min delay is used for launch path and Max delay for capture path c. Both Max delay is used for launch and Capture path d. Both Min delay is used for both Capture and Launch paths * 19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called. a. Utilization b. Aspect Ratio c. OCV fivteme Ratio * 20) The Solution for Antenna effect is _. t Diode insertion b. Shielding c. Buffer insertion d. Double spacing * 21) To avoid cross talk, the shielded net is usually connected to__. 8. VDD R. VSS c. Both VDD and VSS d, Clock + 22)If the data is faster than the clock in Reg to Reg path __ viol jon may come. 4. Solupp Hold. Boh d, None + 23) Hold violations are preferred to fix_. 4. Before placement b, Aor placement Before CTS 4 Aor CTS + 24) Which of the following is not present in SDC_? a, Max ran b, Max cap ¢, Max fanout d. Max current density + 25) Timing sanity check means (with respect to PD) a, Checking timing of routed design with out net delays b. Checking Timing of placed design with net delays ¢. Checking Timing of unplaced design without net delays d. Checking Timing of, routed design with net delays * 26) Which of the following is having highest priority at final stage (post routed) of the design 6. Setup violation b. Hold vilationo. Skew d, None * 27) Which of the following is best suited for CTS? @. CLKBUF b. BUF c. INV d. CLKINV * 28) Max voltage drop will be there at(with out macros) _.4. Let and ight sides b. Bottom and Top sides q Mile d, None * 29) Which of the following is preferred while placing macros _? a, Macros placed center of the die b. Macros placed left and right side of die c. Macros placed bottom and top sides of die d. Macros placed based on connectivity of the I/O. * 30) Routing congestion can be avoided by__. placing cells closer b. Placing cells at comers ¢. Distributing cells d. None + 31) Pitch of the wire is__. ‘a. Min width b. Min spacing c. Min width - min spacing Mi width + min spacing * 32)In Physical Design following step is not there _. a, Floorpianing b. Placement c, Design Synthasis d, CTS » * 33) In technology file if 7 metals are there then which metals you will use for power? a, Metal and metal2 b. Metal3 and metald c, MetalS and metal6 d, Metalé and metal7, * 34) If metal6 and metal? are used for the power in 7 metal layer process design then which metals you will use for clock ? a. Metal and metal2 b. Metal3 and metald c Metald and metals d, Metalé and metal iN * 35) Ina reg to reg timing path Telocktog delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be __. 8. sb, ns Ss 6s * 36) Difference between Clock bufflinverters and normal bufflinverters is a. Clock buftfinverters are faster than normal buff/inverters b. Clock buff/inverters are slower than normal bufffinverters ¢. Clock buffinverters are having equal rise and fal times with high drive strengths compare tfhormal butfinverters d. Normal but/inverters are having equal rise and fall times with high drive/strengths compare to Clock but/inverters. * 37) Which configuration is more preferred during floorplaning ? '2. Double back with flipped rows b, Double back with non flipped rows c. With channel spacing between rows and no double back d. With channel spacing between rows and double back + 38) What is the effect of high drive strength buffer when added in long net? a. Delay on the net increases b. Capacitance on the net increases &. Delay on the net decreases d. Resistance on the net increases.* 39) Delay of a cell depends on which factors 7 2, Output transition and input load B. Input transition and Output load c. Input transition and Output transition d. Input load and Output Load. * 40) After the final ro jing the violations in the design _. a, There can be no setup, no hold violations b, There can be only setup violation but no hold c. ‘There can be only hold violation not Setup violation d. There can be both violations. © 41) Utilisa nn of the chip after placement optimisat will be. 4. Constant b, Decrease Ioreased. None ofthe hove * 42) What is routing congestion in the design? 2. Ratio of required routing tracks to available routing tracks b. Ratio of available routing tracks to required routing tracks c. Depends on the routing layers available d, None of the above * 43) What are preroutes in your design? ‘4. Power routing b. Signal routing c, Power and Signal routing d. None of the above. * 44) Clock tree doesn't contain following cell _. v a. Clock buffer b. Clock Inverter ¢, AOI cell d, None of the above © Answers: ‘Yb 2) 3)b 4)e 8)b 6)d 7)a 8)c 9)d 10)b 11)d 12)d 13)b 14)c 15)b 16)a 17)c 18)a 19)¢ 20)a 21)b 22)b 23)d 24}d 25)e 26)d 27)a 28)e 29)d 30)c 31}d 32)e 33}! 34)e 35)d 36)e 37)a 38)c 39)b 40)d 41)e 42)a 43)2 44) CMOS Design Interview Questions Below are the important VLSI CMOS interview questions. This set of interview questions may be updated in future, Answers will be posted one by one as and when i prepare them | Readers are encouraged to post answers in comment section. Here we go. Draw Vds-Ids curve for an MOSFET. How it varies with a) increasing Vgs b)velocity saturation )Channel length modulation d)WiL ratio. What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs? What is latch-up in CMOS design and what are the ways to prevent it? What is Noise Margin? Explain with the help of Inverter. What happens to delay if you increase load capacitance? Give the various techniques you know to minimize power consumption for CMOS logic? What happens when the PMOS and NMOS are interchanged with one another in an inverter? What is body effect? Why is NAND gate preferred over NOR gate for fabrication? What is Noise Margin? Explain the procedure to determine Noise MarginWhat happens to delay if we include a resistance at the output of a CMOS circuit What are the limitations in increasing the power supply to reduce delay? How does Resistance of the metal lines vary with increasing thickness and increasing length? What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus? 2 why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter? Give the expression for CMOS switching power dissipation? Why is the substrate in NMOS connected to ground and in PMOS to VDD? What is the fundamental difference between a MOSFET and BJT ? Which transistor has higher gain- BJT or MOS and why? Why PMOS and NMOS are sized equally in a Transmission Gates? What is metastabllity? When/why it will occur? What are the different ways to avoid this? -xplain zener breakdown and avalanche breakdown? Expiain sizing of the inverter? How do you size NMOS and PMOS transistors to increase the threshold voltage?, * What happens if Vis is increased over saturation?” In the I-V characteristics curve, why is the saturation curve flat or constant? ‘What happens if a resistor is added in series with the drain in a CMOS transistor? <——_ What are the different regions of operation in a CMOS transistor? What are the effects of the output characteristics for a change in the beta (B) value? What is the effect of body bias? What is hot electron effect and how can it be eliminated? What is channel length modulation? What is the effect of temperature on threshold voltage? What is the effect of temperature on mobility? What is the effect of gate voltage on mobility? What are the different types of scaling? What is stage ratio? << eeeFfefF What is charge sharing on a bus? What is electron migration and how can it be eliminated? Can both PMOS and NMOS transistors pass good 1 and good 0? Explain. Why is only NMOS used in pass transistor logic? What are the different methodologies used to reduce %rge sharing in dynamic logic? What is meant by clock race? What is meant by single phase and double phase clo if given a choice between NAND and NOR gates, whic'*ure would you pick? Explain Explain the origin ofthe Various capacitances in the CMOS transistor and the physical reasoning behind it Why should tre number of CMOS transistors that are connected in series be reduced? < \Whatis charge sharing between bus and memory element?<——— What is crosstalk and how can itbe avoided? Realize an XOR gate using NAND gate. <— What are the advantages and disadvantages of Bi-CMOS process?), <—— Draw an XOR gate with using minimum number of transistors and explain the operation, <— What are the ertical parameters in a latch and fipsiop? Whats the significance of sense amplifier in an SRAM? <—— Explain Domino logic. <—— What are the advantages of depletion mode devices over the enhancement mode devices? <— How can the rise and fall mes in an inverter be equated?What is meant by leakage current? Realize an OR gate using NAND gate. Realize an NAND gate using a 2:1 multiplexer Realize an NOR gate using a 2:1 multiplexer. Draw the layout ofa simpie inverter. What are the substrates of PMOS and NMOS transistors connected to and explain the results i the connections are interchanged with the other. What are repeaters? << What is tunneling problem? What is meant by negative biased instability and how can it be avoided? <—— What is Elmore delay algorithm? What is meant by metastabilty? What isthe effect of Vdd on delay? What is the effect of delay, rise and fall times with increase in load capacitance? <~ What is the value of mobiity of electrons? What is value of mobiity of holes? Give insights of an inverter. Draw Layout, Explain the working * Give insights of a 2 input NOR gate, Draw Layout. Explain the working Give insights of a 2 input NAND gate. Draw layout. Explain the working? Implement F= not (AB+CD) using CMOS gates. What is a pass gate. Explain the working? Why do we need both PMOS and NMOS transistors to implement a pass gate? What does the above code synthesize to? Draw cross section of a PMOS transistor. Draw cross section of an NMOS transistor. What is a D-ateh? Implement D fip-fop with a couple of latches? Implement a 2 input AND gate using transmission gate? <—— Explain various adders and difference between thom? How can you construct both PMOS and NMOS on a single substrate? What happens when the gate oxide is vary thin? What is SPICE? What are the diferences between IRSIM and SPICE? <—— What ae the differences between netist of HSPICE and Spectre? <— Implement F = AB+C using CMOS gates? What is hot electron effect? Detine threshold voltage’? List out the factors affecting power consumption on @ chip? What r the phenomenon which come into play when the devices are scaled to the sub- micron lengths? What is clock feed through? <— Implement an Inverter using a single transistor? <— What is Fowler-Nordheim Tunneling? << Which gate is normally prefered while implementing circuits using CMOS logic, NAND or NOR? Why? Draw the Differential Sense Ampltier and exolain its working. How to size ths circuit? <— What happens i we use an Inverter instead of the Differential Sense Amplifier? << Draw the SRAM Write Circuitry <—— How did you arrive at sizes of transistor in SRAM? <—— How does the size of PMOS pull up transistors for bit and bitbar lines affect SRAM's. <~ performance? Whats the excel path in @ SRAM?Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock <— signal? Give a big picture of the entire SRAM layout showing placements of SRAM cells, row << decoders, column decoders, read circuit, write circuit and bulfers, Ina SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? < Design For Test-DFT Answer: For designs with both positive and negative clocked flops, the scan insertion too! will always route the scan chain so that the negative clocked flops come before the positive edge flops in the chain. This avoids the need of lockup latch. For the same clock domain the negedge flops will always capture the data just captured into the posedge flops on the posedge of the clack. For the multiple clock domains, it all depends upon how the clock trees are balanced. If the clock domains are completely asynchronous, ATPG has to mask the receiving flops. What you mean by scan chain reordering? ‘Answert Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsis and can reorder to optimize it... it maintains the number of flops in a chain. ‘Answer2: During placement, the optimization may make the scan chain dificult to route due to congestion. Hence the tool will re-order the chain to reduce congestion, This sometimes increases hold time problems in the chain. To overcome these buffers may have tobe inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap call from different clock domains. Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new net list. what are the differences between SIMULATION and SYNTHESIS Simulation verify your design. synthesis <= Check for your timing Simulation is used to verify the functionality of the circuit... a)Functional‘Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met. ‘Synthesis:One of the foremost in back end steps where by synthesizing is nothing 19 VHDL or VERILOG description to @ set of primitives(equal PLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components but conve ns as Can u tell me the differences between latches & flipflops? ‘There are 2 types of circuits: 1, Combinational 2. Sequential Latches and flipflops both come under the category of "sequential circuits", whose output depends not only on the current inputs, but also on previous inputs and outputs. Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1) Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, output won't change immediately. At time = 3 seconds, clock transition takes place. After that, 0/P will change, Flip-flops are of 2 types: L Positive edge triggered 2. negative edge triggered 1)fllipflops take twice the nymber of gates as latches 2) so automatically delay is more for flipflops 3)power consumption is also more latch does not have a clock signal, whereas a flip-flop always does. What is slack? ‘The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path. Slack may be +ve or -ve.Equivalence between VHDL and €2 << ‘There is concept of understanding in C there is structure.Based upon requirement structure provide facility to store collection of different data types. In VHDL we have direct access to memory so instead of using pointer in C (and member of structure) we can write interface store data in memory and access it. RTL and Behavioral Register transfer language means there should be data flow between two registers and logic is in between them for end registers data should flow. Behavioral means how hardware behave determine the exact way it works we write using HDL syntax.For complex projects it is better mixed approach or more behavioral is used. VHDL QUESTIONS 1. What is the difference between using direct instantiations and component ones except that you need to declare the component? 2. What is the use of BLOCKS? 3. What is the use of PROCEDURES? 4. What is the usage of using more then one architecture in an entity? 5. What is a D-latch? Write the VHDL Code for it? 6. Implement D flip-flop with @ couple of latches? Write @ VHDL Code for a D flip- flop? 7. Differences between Signals and Variables in VHDL? If the same code is written using Signals and Variables what does it synthesize to? Differences between functions and Procedures in VHDL? Explain the concept of @ Clock Divider Circuit? Write a VHDL code for the same? Digital Design interview questions: 1. Give two ways of converting a two input NAND gate to an inverter << 2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random <—— Signal Generator; you can expect any sequential ckt)3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? <—— Give a circuit to divide frequency of clock cycle by two Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the. <——— Clock) 6. Suppose you have 2 combinational circuit between two registers driven by ag clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors) 7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied? dealy increase + Pdecrease->delay decrease + Vincrease->delay decrease + Videcrease->delay increase + Tincrease->delay increase + Tdecrease->delay decrease Explain the flow of physical design and inputs and outputs for each step in flow. Physical Design Flow ‘The physical design flow is generally explained in the Figure (1.). In each section of the flow EDA tools available from the two main EDA companies-Synopsys and Cadence is also listed. In each and every step of the flow timing and power analysis, can be carried out. If timing and power requirements are not met then either the whole flow has to be re-exercised or going back one or two steps and optimizing the design or incremental optimization may meet the requirementsWhat is cell delay and net delay? Gate delay Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output [Magma] Gate delay =function offip transition time, Cnet+Cpin). Cell delay is also same as Gate delay. Cell delay For any gate it is measured between 50% of input transition to the corresponding 50% of output transition Intrinsic delay Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition. It is predominantly caused by the internal capacitance associated with its transistor.* This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors. * Net Delay (or wire delay) * The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. * Its due to the finite resistance and capacitance of the net Its also known as wire delay. © Wire delay =fn(Rnet , Cnet*Cpin) ‘What are delay models and what is the difference between them? * Linear Delay Model (LDM) * Non Linear Delay Model (NLDM) What is wire load model? * Wire load model is NLDM which has estimated R and C of the net. Why higher metal layers are preferred for Vdd and Vss? * Because it has less resistance and hence leads to less IR drop. What is logic optimization and give some methods of logic optimization. * Upsizing * Downsizing * Buffer insertion * Buffer relocation * Dummy butter placement ‘What is the significance of negative slack? * negative slack==> there is setup voilation==> deisgn can fall What is signal integrity? How it affacts Timing? ——————™” * IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues. * If ldrop is more==>delay increases.+ crosstal there can be setup as well as hold voilation What is IR drop? How to avoid? How it affects timing? * There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.1R drop. + IFIR drop is more==>delay increases. What is EM and it effects? * Due to high current fow in the metal atoms of the metal can displaced from its origia place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration. + Affects: Either short or open of the signal ine or power line. What are types of routing? * Global Routing + Track Assignment + Detail Routing What is latency? Give the types? << $$$___ * Source Latency * itis known as source latency also. It the clock definition point in the design defined as "the delay from the clock origin point to * Delay from clock source to beginning of clock tree ([.¢. clock definition point). * The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design * Network latency * tis also known as Insertion delay or Network latency. Itis defined as "the delay from the clock definition point to the clock pin of the register * The time clock signal (ise or fall) takes to propagate from the clock definition point to a register clock pin ‘What is track assignment? * Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.What is congestion? * Ifthe number of routing tracks available for routing is less than the required tracks then it is known as congestion. Whether congestion is related to placement or routing? + Routing What are clock trees? + Distribution of clock from the clock source to the syne pin of the registers What are clock tree types? § <@$£$—@$@$ + Hiroe, Balanced tree, X tree, Clustering tree, Fish bone Whatiselning and butting? * Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell * Buffering is a method of optimization that is used to insert betffers in high fanout nets to decrease the dealy, asic Different Types of Delays in ASIC or VLSI design * Source Delay/Latency * Network Delay/Latency + Insertion Delay + Path Delay * Net delay, wire delay, interconnect delay* Propagation Delay + Phase Delay + Cell Delay * Intrinsic Delay + Extrinsic Delay * Input Delay * Output Delay + ExitDelay * Latency (Pre/post CTS) + Uncertainty (Pre/Post CTS) + Unateness: Positive unateness, negative unateness * Jitter: PLL jitter, clock jitter Gate delay * Transistors within a gate take a finite time to switch, This means that a change on the input of a gate takes a finite time to cause a change on the output [Magma] * Gate delay =function of{ip transition time, Cnet+Cpin). * Coll delay is also same as Gate delay. Source Delay (or Source Latency) * Its known as source latency also. It the clock definition point in the design defined as "the delay from the clock origin point to * Delay from clock source to beginning of clock tree (|.2, clock definition point). * The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design Network Delay(latency) * tis also known as Insertion delay or Network latency. Itis defined as "the delay from the clock definition point to the clock pin of the register’.+ The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin Insertion delay $A» * The delay from the clock definition point to the clock pin of the register. Transition delay * tis also known as "Siew". Its defined as the time taken to change the state of the signal Time taken for the transition fram logic 0 to logic 1 and vice versa . or Time taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa * Transition is the time it takes for the pin to change state, slew << + Rate of change of logic.See Transition delay + Siew rate is the speed of transition measured in volt ns Rise Time * Rise time is the difference between the time when the signal crosses a low threshold to the time when the signal crosses the high threshold. It can be absolute or percent. * Low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settied voltage level. Fall Time * Fall ime is the difference between the time when the signal crosses a high threshold to the time when the signal crosses the low threshold. * The low and high thresholds are fixed voltage levels around the mid voltage level or it can be either 10% and 90% respectively or 20% and 80% respectively. The percent levels are converted to absolute voltage levels at the time of measurement by calculating percentages from the difference between the starting voltage level and the final settled voltage level, * For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric triangular wave, this is reduced to just 50%. + The rise/fall definition is set on the meter to 10% and 90% based on the linear power in Watts, These points translate into the -10 dB and -0.5 dB points in log mode (10 log 0.1) and (10 log 0.9). The rise/fall time values of 10% and 90% are calculated based on an algorithm, which looks at the mean power above and below the 50% points of the rise/fall times.+ Path delay * Path delay is also known as pin to pin delay. Its the delay fram the input pin of the cell to the output pin of the cell Net Delay (or wire delay) * The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. * Itis due to the finite resistance and capacitance of the net.lts also known as wire delay. © Wire delay =fn(Rnet , Cnet+Cpin) Propagation delay + For any gate itis measured between 50% of input transition to the coresponding 50% of output transition * This is the time required for a signal to propagate through a gate or net. For gates itis the time it takes for a event at the gale input to affect the gate output. * For netitis the delay between the time a signal is frst applied to the net and the time it reaches other devices connected to that net + Itis taken as the average of ise time an fal time ie. Tpd= (TphitTplhy2 Phase delay < + Same as insertion delay Cell delay + For any gate itis measured between 50% of input transition to the coresponding 50% of output transition Intrinsic delay * Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell * Its defined as the delay between an input and output pair of a cell, when @ near zero slew is applied to the input pin and the output does not see any load condition. Its predominantly caused by the internal capacitance associated with its transistor. * This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors. Extrinsic delay+ Same as wire delay, net delay, interconnect delay, flight time. * Extrinsic delay is the delay effect that associated to with interconnect. output pin of the cell to the input pin of the next ce! Input delay * Input delay is the time at which the data arrives at the input pin of the block from external circuit with respect to reference clock. Output delay * Output delay is time required by the external circult before which the data has to arrive at the output pin of the block with respect to reference clock. Exit delay * Its defined as the delay in the longest path (critical path) between clock pad input and an output. It determines the maximum operating frequency of the design Latency (pre/post cts) * Latency is the summation of the Source latency and the Network latency. Pre CTS estimated latency will be considered during the synthesis and after CTS propagated latency is considered Uncertainty (prefpost cts) * Uncertainty is the amount of skew and the variation in the arrival clock edge, Pre CTS uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew + Jitter. Unateness * Atunction is said to be unate if the rise transition on the positive unate input variable causes the ouput to rise or no change and vice versa * Negative unateness means cell output logic is inverted version of input logic. eg. In Inverter having input A.and output Y, Y is -ve unate w.rto A. Positive unate means cell ‘output logic is same as that of input * These +ve ad -ve unateness are constraints defined in library file and are defined for ‘output pin war:to some input pin. * Aclock signal is positive unate if rising edge at the clock source can only cause a rising edge at the register clock pin, and a falling edge at the clock source can only cause a faling edge at the register clock pin. * Aclock signal is negative unate y fa rising edge at the clock source can only cause @ falling edge at the register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock pin. In other words, the clock signal is inverted,* Aclock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the clock path, For example, a clock that passes through an XOR gate is not unate because there are nonunate arcs in the gate, The clock sense could be either positive or negative, depending on the state of the other input to the XOR gate. * The short-term variations of a signal with respect to its ideal position in time. * Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value. * From cycle to cycle the period and duty cycle can change slightly due to the clock generation circultry. This can be modeled by adding uncertainty regions around the rising and falling edges of the clock waveform, Sources of Jitter Common sources ofitterinciudes§ <—— SD < * Skew can be positive or negative.* When data and clock are routed in same direction then it is Posit 0 skew. + When data and clock are routed in opposite then itis negative skew. Recovery Time | << * Recovery specifies the minimum time that an asynchronous control input pin must be held stable after being de-asserted and before the next clock (active-edge) transition. * Recovery time specifies the time the inactive edge of the asynchronous signal has to arrive before the closing edge of the clock * Recovery time is the minimum length of time an asynchronous control signal (eg.preset) must be stable before the next active clock edge. The racovary slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals. Equation 1: * Recovery Slack Time = Data Required Time 4€" Data Arrival Time * Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tekq* Register to Register Delay * Data Required Time = Latch Edge + Clock Network Delay to Destination Register =Tsetup Ifthe asynchronous control is not registered, equations shown in Equation 2 is used to calculate the recovery slack time. Equation 2: * Recovery Slack Time = Data Required Time a€* Data Arrival Time * Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay * Data Required Tim« Delay+Tsetup Latch Edge + Clock Network Delay to Destination Register + Ifthe asynchronous reset signal is from a port (device 1/0), you must make an Input Maximum Delay assignment to the asynchronous reset pin to perform recovery analysis con that path Removal Time. <—————— * Removal specifies the minimum time that an asynchronous control input pin must be held stable before being de-asserted and after the previous clock (active-edge) transition. * Removal time specifies the length of time the active phase of the asynchronous signal has to be held after the closing edge of clock,Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. Calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals, If the asynchronous control is registered, equations shown in Equation 3 is used to calculate the removal slack time. Ifthe recovery or removal minimum time requirement is violated, the output of the sequential celi becomes uncertain. The uncertainty can be caused by the value set by the resetbar signal or the value clocked into the sequential cell rom the data input. Equation 3 Removal Siack Time = Data Arrival Time 4€° Data Required Time: Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tokq of Source Register + Register to Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register + Thold Ifthe asynchronous control is not registered, equations shown in Equation 4 is used to calculate the removal slack time. Equation 4 Removal Slack Time = Data Arrival Time &€° Data Required Time Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay Data Required Tim Latch Edge + Clock Network Delay to Destination Register +Thold Ifthe asynchronous reset signal is from a device pin, you must specify the Input Minimum, Delay constraint to the asynchronous reset pin to perform a removal analysis on this, path. ‘What is the difference between soft macro and hard macro? or ‘What is the difference between hard macro, firm macro and soft macro? << What are IPs? Hard macro, firm macro and soft macro are all known as IP (|ntellectual property). They are optimized for power, area and performance, They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible forall type of ASIC. implementation. Hard macro can be used in pure ASIC design flow, not in FPGA flow. Before bying any IP itis very important to evaluate its advantages and disadvantages over each other, hardware compatibility such as /O standards with your design blocks, reusability for other designs.Soft macros es * Soft macros are in synthesizable RTL. * Soft macros are more flexible than firm or hard macros. * Soft macros are not specific to any manufacturing process, * Soft macros have the disadvantage of being somewhat unpredictable in terms of performance, timing, area, or power. * Soft macros carry greater IP protection risks because RTL source code is more portable and therefore, less easily protected than either a netlist or physical layout data. * From the physical design perspective, soft macro is any cell that has been placed and routed in a placement and routing tool such as Astro. (This is the definition given in Astro. Rail user manual !) * Soft macros are editable and can contain standard cells, hard macros, or other soft macros. Firm macros <— * Firm macros are in netlist format * Firm macros are optimized for performance/area/power using a specific fabrication technology. * Firm macros are more flexible and portable than hard macros. * Firm macros are predictive of performance and area than soft macros. Hard macro <— * Hard macros are generally in the form of hardware IPs (or we termed it as hardwre IPS !). * Hard macos are targeted for specific IC manufacturing technology. * Hard macros are block level designs which are silicon tested and proved. * Hard macros have been optimized for power or area or timing, * Inphysical design you can only access pins of hard macros unlike soft macros which allows us to manipulate in different way. * You have freedom to move, rotate, flip but you can't touch anything inside hard macros. * Very common example of hard macro is memory. It can be any design which carries dedicated single functionality (in general)...for example it can be a MP4 decoder.* Be aware of features and characteristics of hard macro before you use it in your design other than power, timing and area you also should know pin properties like sync pin, YO. standards ete + LEF, GDS2 file format allows easy usage of macros in different tools. From the physical design (backend) perspective: © Hard macro is a block that is generated in a methodology other than place and route (i.e. Using full custom design methodology) and is brought into the physical design database (eg. Milkyway in Synopsys; Volcano in Magma) as a GDS? file. What is the difference between FPGA and CPLD?.| << FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device— both are programmable logic devices made by the same companies with different characteristics, "A Complex Programmable Logic Device (CPLD) is a Programmable Logie Device with ‘complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building biock of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations" Arct Granularity is the biggest difference between CPLD and FPGA, FPGAare “fine-grain” devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops, combinational logic and memories. FPGAs offer much higher complexity, up to 150,000 fip-flops and large number of gates available. CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of ‘moderately complicated data processing devices. PALS typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several rnilion, CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with fip-flops and combinational logic. CPLDs based on AND-OR structure. CPLD's have a register with associated logic (AND/OR matrix). CPLD’s are mostly implemented in control applications and FPGA's in datapath applications. Because of this, course grained architecture, the timing is very fixed in CPLDs, + FPGAare RAM based. They need to be "downloaded" (configured) at each power-up. CPLD are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once. FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA,Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases, The FPGA are volatile in many cases and hence they need a configuration memory for working. There are some FPGAs now which are nonvolatile This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory. * The characteristic of non-volatilty makes the CPLD the device of choice in modem digital designs to perform ‘boot loader functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. * Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-lo-output timings than FPGA. Features * FPGAhave special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this. * FPGAcan contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500> * Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where “instant-on", fast and wide decoding, Ultra-tow idle power consumption, and design security are important (e.g. in battery- operated equipment). * Security: In CPLD once programmed, the design can be locked and thus made secure, Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue. * Power: The high static (idle) power consumption prohibits use of CPLD in battery- operated equipment. FPGA idle power consumption is reasonably low, although itis sharply increasing in the newest families. * Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and ‘even on-chip micropracessors and Multi-Gigabit Transceivers. These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage, * Use FPGAS for larger and more complex designs, * FPGAis suited for timing circuit becauce they have more registers , but CPLD is suited for control circuit because they have more combinational circult. At the same time, If you synthesis the same code for FPGA for many times, you will nd out that each timing report is different. But itis different in CPLD synthesis, you can get the same result, As CPLDs and FPGAs become more advanced the differences between the two device types wil continue to blur. While this trend may appear to make the two types more difficult to keep apar, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macrocells with predictable timing characteristics wil likely be sufficient to maintain a product differentiation for the foreseeable future. What is the difference between FPGA and ASIC? |< ‘This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer. FPGAvs. ASIC * Difference between ASICs and FPGAs mainly depends on costs, tool availabilty, performance and design flexibility, They have their own pros and cons but itis designers responsibilty to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs. FPGA * Field Programable Gate Arrays FPGA Design Advantages * Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA! Done !! * No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there, FPGA tools are cheap. (sometimes its ‘ree | You need to buy FPGA.... thats all !). ASIC youpay huge NRE and tools are expensive. | would say "very expensive"...Its in crores...!! * Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less. The FPGA design flow eliminates the ‘complex and time-consuming floorplanning, place and route, timing analysis. + More predictable project cycle: The FPGA design flow eliminates potential re-spins, water capacities, etc of the project since the design logic is already synthesized and verified in FPGA device. + Field Reprogramability: Anew bitstream (i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs stat ‘rom a couple of dollars to several hundreds or more depending on the hardware features. + Reusability: Reusability of FPGA is the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC, Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again. Modern FPGAs are reconfigurable both partially and dynamically. FPGAs are good for prototyping and limited production.{f you are going to make 100-200 ‘boards it isn't worth to make an ASIC.Generally FPGAs are used for lower speed, lower complexity and lower volume designs. But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a host of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of design. + Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed 1/0, embedded CPU etc inbuilt, which can be used to get better performace, Modern FPGAs are packed with features. Advanced FPGAs Usually come with phase-locked loops, low-voltage differential s.gnal, clock data recovery, more internal routing, high speed, hardware mulipiers for DSPs, memory,programmable VO, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xiinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAs available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC 7 + FPGAsythesis is much more easier than ASIC. * InFPGAyou need not do floor-planning, tool can do it efficiently. In ASIC you have do it FPGA Design Disadvantages * Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race | * You have to use the resources available in the FPGA. Thus FPGA limits the design size. * Good for low quantity production. As quantity increases cost per product increases. compared to the ASIC implementation, asic + Application Specific Intergrated Circiut ASIC Design Advantages + Gost...cost...cost...owar unit costs: For very high volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA. + Speed...speed...speed.... ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations. ow power: ASIC can be optimized for requited low power. ‘There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA fails badly !!! Can you think of a cell phone which has to be charged for every call...never....|ow power ASICs helps battery live longer life !! * INASIC you can implement analog circuit, mixed signal designs. This is generally not, possible in FPGA,* InASIC DFT (Design For Test) is inserted, In FPGA DFT is not carried out (rather for FPGA no need of DFT !) ASIC Design Diadvantages + Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC. * Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!) + Expensive Tools: ASIC design tools are very much expensive, You spend a huge amount of NRE. Structured ASICS * Structured ASICs have the bottom metal layers fixed and only the top layers can be: designed by the customer. * Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity. * Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and 1/0. FPGAvs. ASIC Design Flow ComparisonSilicon Process and Library Characteristics What exact process are you using? How many layers can be used for this design? Are the Cross talk Noise constraints, Xtalk Analysis configuration, Cell EM & Wire EM available? Design Characteristics What is the design application? Number of calis (placeable objects)? Is the design Verilog or VHDL? Is the nets flat or hierarchical? Is there RTL avaliable? Is there any datapath logic using special datapath tools? Is the DFT to be considered? Can scan chains be reordered? Is memory BIST, boundary scan used on this design? ‘Ase static timing analysis constraints available in SDC format? Clock Characteristics ‘+ How many clock domains are in the design?© What are the clock frequencies? * Is there a target clock skew, latency or other clock requirements? Does the design have a PLL? Ifs0, is it used to remove clock latency? Is there any 1/0 cell in the feedback path? Is the PLL used for frequency multipliers? ‘Are there derived clocks or complex clock generation circuitry? * Are there any gated clocks? + Ifyes, do they use simple gating elements? * Is the gate clock used for timing or power? * For gated clocks, can the gating elements be sized for timing? * Are you muxing in a test clock or using a JTAG clock? * Available cells for clock tree? Are there any special clock repeaters in the library? ‘Are there any EM, slew or capacitance limits on these repeaters? How many drive strengths are available in the standard buffers and inverters? Do any of the buffers have balanced rise and fall delays? Any there special requirements for clock distribution? * Will the clock tree be shielded? If so, what are the shielding requirements? Floorplan and Package Characteristics + Target die area? * Does the area estimate include power/signal routing? © What gatesimm2 has been assumed? © Number of routing layers? * Any special power routing requirements? + Number of digital VO pins/pads? * Number of analog signal pins/pads? + Number of power/ground pins/pads? * Total number of pins/pads and Location? * Will this chip use a wire bond package? * Will this chip use a flip-chip package? * If Yes, is it /O bump pitch? Rows of bumps? Bump allocation?Bump pad layout guide? * Have you already done floorplanning for this design? * Ifyes, is conformance to the existing floorplan required? © What is the target die size? * What is the expected utilization? * Please draw the overall floorplan ? * Is there an existing floorpian available in DEF? ‘+ What are the number and type of macros (memory, PLL, etc.)? * Ave there any analog blocks in the design? © What kind of packaging is used? Flipchip? * Are the I/Os periphery VO or area VO? * How many VOs? * Is the design pad limited? * Power planning and Power analysis for this design? * Are layout databases available for hard macros ? * Timing analysis and correlatio?Physical verification ? Data Input Library information for new library lib for timing information GDSII or LEF for library cells including any RAMS RTLin Verlog/VHDL format © Number of logical blocks in the RTL. * Constraints for the block in SDC * Floorplan information in DEF * WO pin location * Macro locations ASIC General General ASIC questions are posted here. More questions related to different catagories of ASICs can be found at respective sections. What are the diferences between PALS, PLAs, FPGAs, ASICs and PLDs? In system wih insuffcient hold time, vill slowing down the clock help? In system wih insufcient setup time, wil siowing down the clock help? Why would testbench not have pins (port on it? When declaring a fp flop, why would net you declare its output value inthe port statement? Give 2 advantages of using a script to build a chip? Avi state" bus is direcly connected to a set of CMOS input buffers. No other wires or components are attached tote bus wires. Upon observation we can fn that under certain condlioe, ths ecu is consuming considerable power. Why its 80? Is cut comect?Itnol,hoWw to correct? 's Verilog (or that matter any HDL) is a concurrent or sequential language? Whats the function of sensitiv ist? [Ametly -type state machine is coded using D-ype rising edge fip flops. The reat and clock signals are inthe sensitiv ist but wih one of the next state logic input signals have been loft out ofthe sensi Ist, Explain what happens when the state machine is simulated? Wil the stale machine be synthesized correcly? ‘Amoore -type slate machin is coded using D-type rising edge fp ops. The reset and clock signals are inthe sensitivity ist but with one of the next state logic input signals have been lef out of he sensi Ist Explain what happens when the sate machine is ‘simulated? Will the state machine be synthesized correctly? What type of delay is most Ike a infinite bandwidth transmssion line? Define metastablty. Wen does metastablity occur? Give one exemple ofa situaton where metastabilty could occur Give two ways metastabilty could manifest isl! na state machine What is MTBF? Does MTBF give the time untl the next faire occurs? Give 3 ways in which to reduce the chance of metastable failure, <—————— Give 2 advantages of using a synchronous reset methodology. Give 2 disadvantages of using a synchronous reset methodology* Give 2 advantages of using an asynchronous reset methodology. + Give 2 disadvantages of using an asynchronous reset methodology. * What are the two most fundamental inputs (files) to the synthesis tool? <—_ + What are two important steps in synthesis? What happens in those steps? <———— + What are the two major output (files) from the synthesis process? + Name the fundamental 3 operating consitions that determine (globally) the delay characteristics of CMOS gates. For each how they affect gate delay? + Fora single gate, with global gating conditions held constant , what 3 delay coefficients effect total gate delay? Which is the most sensitve to circult topology? FPGA. What is the difference between FPGA and CPLD? FPGA-Field Programmable Gate Array and CPLD-Complex Programmable Logic Device— both are programmable logic devices made by the same companies with different characteristics. * "AComplex Programmable Logic Device (CPLD) is a Programmable Logic Device with complexity between that of PALs (Programmable Array Logic) and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations” * This is what Wiki defines....!! ture * Granularity is the biggest difference between CPLD and FPGA. + FPGAare "fine-grain" devices. That means that they contain hundreds of (up to 100000) of tiny blocks (called as LUT or CLBs ete) of logic with flip-flops, combinational logic and memories. FPGAs offer much higher complexity, up to 150,000 flip-flops and large number of gates available. + CPLDs typically have the equivalent of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a tew hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several mnilion, CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with fip-flops and combinational logic. CPLDs based on AND-OR structure. CPLD's have a register with associated logic (AND/OR matrix). CPLD’s are mostly implemented in control applications and FPGA's in datapath applications. Because of this, course grained architecture, the timing Is very fixed in PLDs. FPGA are RAM based. They need to be "downloaded" (configured) at each power-up, CPLD ‘are EEPROM based. They are active at power-up i.e. as long as they've been programmed at least once,FPGA needs boot ROM but CPLD does not. In some systems you might not have enough time to boot up FPGA then you need CPLD+FPGA. * Generally, the CPLD devices are not volatile, because they contain flash or erasable ROM memory in all the cases. The FPGA are volatile in many cases and hence they need a configuration memory for working, There are some FPGAs now which are nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory. * The characteristic of non-volatilty makes the CPLD the device of choice in modem digital designs to perform ‘boot loader functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. * Because of coarse-grain architecture, one block of logic can hold a big equation and hence CPLD have a faster input-lo-output timings than FPGA. Features + FPGAhave special routing resources to implement binary counters,arithmetic functions like adders, comparators and RAM. CPLD don't have special features like this. * FPGAcan contain very large digital designs, while CPLD can contain small designs only.The limited complexity (<500> * Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide input functions. Use CPLDs for small designs, where “inslant-on", fast and wide decoding, ultra-low idle power consumption, and design security are important (e.g., in battery operated equipment). * Security: In CPLD once programmed, the design can be locked and thus made secure, Since the configuration bitstream must be reloaded every time power is re-applied, design security in FPGA is an issue. * Power: The high static (idle) power consumption prohibits use of CPLD in battery- operated equipment. FPGA idle power consumption is reasonably low, although itis sharply increasing in the newest families. Design flexibility: FPGAs offer more logic flexibility and more sophisticated system features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even (on-chip microprocessors and Multi-Gigabit Transceivers. These benefits and opportunities of dynamic reconfiguration, even in the end-user system, are an important advantage, * Use FPGAS for larger and more complex designs, + FPGAis suited for timing circuit becauce they have more registers , but CPLD is sulted ‘for control circuit because they have more combinational circuit. At the same time, If you synthesis the same code for FPGA for many times, you will nd out that each timing report is different. But itis different in CPLD synthesis, you can get the same result ‘As CPLDs and FPGAs become more advanced the differences between the two device types wil continue to blur. While this trend may appear to make the two types more difficult to keep apart,the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics wil likely be sufficient to maintain a product differentiation for the foreseeable future. ‘What is the difference between FPGA and ASIC? * This question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subjact reveals the fact that there are lot of thinks to be understood !! So here is the answer. FPGAvs. ASIC * Difference between ASICs and FPGAs mainly depends on costs, tool availabilty, performance and design flexibility. They have their own pros and cons but itis designers responsibilty to find the advantages of the each and use either FPGA or ASIC for the product. However, recent developments in the FPGA domain are narrowing down the benefits of the ASICs FPGA * Field Programable Gate Arrays * Faster time-to-market: No layout, masks or other manufacturing steps are needed for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA! Done I! * No NRE (Non Recurring Expenses): This cost is typically associated with an ASIC design. For FPGA this is not there, FPGA tools are cheap. (sometimes its ‘ree | You need to buy FPGA... thats all !). ASIC youpay huge NRE and tools are expensive. | would say "very expensive"...Is in crores...!! * Simpler design cycle: This is due to software that handles much of the routing, placement, and timing. Manual intervention is less. The FPGA design flow eliminates the complex and time-consuming floorplanning, place and route, timing analysis. + More predictable project cycle: The FPGA design flow eliminates potential re-spins, wafer capacities, etc of the project since the design logic is already synthesized and verified in FPGA device. * Field Reprogramability: A new bitstream (i.e. your program) can be uploaded remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take $50,000 and more than 4-6 weeks to make the same changes. FPGA costs start rom a couple of, dollars to several hundreds or more depending on the hardware features, Reusability: Reusability of FPGAis the main advantage. Prototype of the design can be implemented on FPGA which could be verified for almost accurate results so that it can be implemented on an ASIC. Ifdesign has faults change the HDL code, generate bit stream, program to FPGA and test again. Modern FPGAs are reconfigurable both partially and dynamically * FPGAs are good for prototyping and limited production. If you are going to make 100-200 boards it isn't worth to make an ASIC.* Generally FPGAs are used for lower speed, lower complexity and lower volume: designs.But today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic density increases and a hast of other features, such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price, FPGAs are Suitable for almost any type of design. * Unlike ASICs, FPGA's have special hardwares such as Block-RAM, DCM modules, MACs, memories and highspeed I/O, embedded CPU ete inbuilt, which can be used to get better performace, Modern FPGAs are packed with features. Advanced FPGAs Usually come with phase-locked loops, low-voltage differential signal, clock data recovery, more internal routing, high speed, hardware multipliers for DSPs, memory,programmable WO, IP cores and microprocessor cores. Remember Power PC (hardcore) and Microblaze (softcore) in Xilinx and ARM (hardcore) and Nios(softcore) in Altera. There are FPGAS available now with built in ADC ! Using all these features designers can build a system on a chip. Now, dou yo really need an ASIC ? + FPGAsythesis is much more easier than ASIC. * InFPGA,you need not do floor-planning, tool can do it efficiently. In ASIC you have do it. FPGA Design Disadvantages * Powe consumption in FPGA is more. You don't have any control over the power optimization. This is where ASIC wins the race | * You have to use the resources available in the FPGA. Thus FPGA limits the design size, * Good for low quantity production. As quantity increases cost per product increases. compared to the ASIC implementation, ASIC Application Specific Intergrated Circiut ASIC Design Advantages Cost....cost...cost.... ower unit costs: For very high Volume designs costs comes out to be very less. Larger volumes of ASIC design proves to be cheaper than implementing design using FPGA. + Speed...speed...speed.... ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity for speed optimizations. * Low power....Low power....Low power: ASIC can be optimized for required low power. ‘There are several low power techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are available to achieve the power target. This is where FPGA tails badly Il! Can you think of a cell phone which has to be charged for every call...never...|ow power ASICs helps battery live longer life !! * INASIC you can implement analog circuit, mixed signal designs. This is generally not possible in FPGA.* InASIC DFT (Design For Test) is inserted, In FPGA DFT is not carried out (rather for FPGA no need of DFT !) ASIC Design Diadvantages + Time-to-market: Some large ASICs can take a year or more to design. A good way to shorten development time is to make prototypes using FPGAs and then switch to an ASIC. * Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues and many more. In FPGA you don't have all these because ASIC designer takes care of all these. ( Don't forget FPGA isan IC and designed by ASIC design enginner !!) + Expensive Tools: ASIC design tools are very much expensive, You spend a huge amount of NRE. Structured ASICS * Structured ASICs have the bottom metal layers fixed and only the top layers can be: designed by the customer. * Structured ASICs are custom devices that approach the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity. * Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and 1/0. FPGA Interview Questions ‘What is minimum and maximum frequency of DCM in spartan-3 series FPGA? List some of constraints you used and their purpose during your design? What is the size of bitmap with changing gate count? What are different types of FPGA programming modes? How to change from one to another? List out some important features of FPGA. List out some of synthesizable and non synthesizable constructs? Draw general structure of FPGA? What is the difference between FPGA and CPLD? What is DCM? Why they are used? Draw FPGA design flow. Explain each step. What is input and output from each step? What is slice, CLB, LUT? Is it possible to configure CLB as RAM? What is purpose of a constraint fle? What is its extension? How you will choose an FPGA? How clock is routed through out FPGA? What are difference between PLL and DLL? What is soft processor? < $< What is hard processor?