Instruction Set category

• Instruction Set is categorized into types based on

•

• Operation performed
• number of operand addresses
• and addressing modes.
• Based on number of operand address in the
instruction.
•

• 4 Address Instruction
• 3 Address Instruction
• 2 Address Instruction
• 1 Address Instruction
• 0 Address Instruction
How to Evaluate the Arithmetic statement in
ZERO,ONE,TWO,THREE Address
• SYMBOLS- ADD,SUB,MUL,DIV for arithmetic
operations
• MOVE –for Transfer type Operation
• LOAD and STORE for transfers to and from Memory
and AC registers
Three Address Instruction
• Each address field to Specify either a
Processor Register or Memory Operand

• Eg: Cyber 170

Two Address Instruction
• Move Instruction
Moves or transfers
the operands to
and from memory
And processor
Registers
One Address Instruction
• USES AC
Accumulator reg
AC <- M[A]
AC <- AC+ M[B]
M[T]<- AC
AC <- M [C]
AC<- AC+ M[D]
AC <- AC * M[T]
M[X]<- AC
T -Temporary Location
Zero Address Instruction
• Do not use
Address Field for
Instruction
TOS<- A
TOS <-B
TOS<- A+B
TOS<- C
TOS<-D
TOS<-C+D
TOS<-(C+D)* (A+B)
M[X]<- TOS
 Calculation of Memory traffic

Assumptions
24-bit memory address (3 bytes)
128 instructions (7 bits rounded to 1 byte)
4 –address Instruction
• Because of the large instruction word size and
number of memory accesses ,the 4- address
machine and instruction format is not seen in the
machine design.
•
Although the 4-address structure is used internally
in some implementations of computer control
units. This kind of controller implementations is
known as micro
coded Control.
•
3-Address instruction:
•

•
Address of next instruction kept in processor state register—the PC (Except
for explicit Branches/Jumps)
•
Rest of addresses in instruction
•
This Instruction will require 3X3+1= 10 bytes to encode a 3-address ALU
instruction.
•

•
The number of memory access are required for a 3-address
instruction:
•
Four words will be transferred to the CPU when the instruction itself is
fetched.= 4
•
Then the two words representing the operands themselves need to be
fetched into the CPU = 2
•
And after the addition has been performed, the result needs to be written
back to memory = 1
Total =07
•
2-address Instruction :
•

•
Result overwrites Operand 2
•
Needs only 2 addresses in instruction but less choice in placing data
•
This Instruction will require 2X3+1= 7 bytes to encode a 2-address ALU
instruction.
•

•
The number of memory access are required for a 2-address
instruction:
•
Three words will be transferred to the CPU when the instruction itself
is fetched. = 3
•

•
Then the two words representing the operands themselves need to be
fetched into he CPU and after the addition has been performed, Result
overwrites Operand =3
•
Total= 06
•
add Op1Addr Op2Addr
•
1-address Instruction :
•

•
Special CPU register, the accumulator, supplies 1 operand and stores result
• One memory address used for other operand
•
Need instructions to load and store operands:
•
•
LDA OpAddr
•
STA OpAddr
•
This Instruction will require 1X3+1= 4 bytes to encode a 1-address ALU
instruction

The number of memory access are required for a 1-address instruction:

•

•
Two words will be transferred to the CPU when the instruction itself is fetched = 2
• Then the one word representing the operand itself need to be fetched into
the CPU register and the accumulator, supplies 1 operand and stores
result = 1
•

•
Total=03
0-Address Instruction
 Comparisons
Instruction Memory Memory M/As to M/As to Memory
Type To Store To Encode fetch an Execute an Traffic
in Bytes in Bytes Instruction Instruction

4-address 5 x 3 = 15 1+(4 x 3) = 13 5 3 5+3=8

3-Address 4 x 3 = 12 1+(3 x 3) = 10 4 3 4+3=7
2-Address 3 x 3 = 09 1+(2 x 3) = 07 3 3 3+3=6
1-Address 2 x 3 = 06 1+(1 x 3) = 04 2 1 2+1=3
0-Address 1 x 3 = 03 1+(0 x 3) = 01 1 0 1+0=1
 Problems
• Evaluate a = (b+c)*d – e in 3-, 2-, 1-, 0- address machines and
compute the memory traffic. Assume 24 bit memory address and
one byte opcode.
3-address 2-address 1-address 0-address Memory traffic for 3-address
Machine: 7 * 3 = 21

add a,b,c load a,b Load b Push b Memory traffic for 2-address
mul a,a,d Add a,c Add c Push c Machine: 6 * 4 = 24
sub a,a,e Mul a,d Mul d Sub Add Push
Memory traffic for 1-address
Sub a,e e Store a d Mul
Machine: 3 * 5 = 15
Push e
Sub Pop a Memory traffic for 0-address
Machine: 3 * 5 + 3 = 18
 Memory Memory M/As to M/As to Memory
to Store to encode Fetch Execute Traffic
add a, b, c ab+c 4*3=12 1+(3*3)= 4 3 4+3=7
mpy a, a, d aa*d
10
sub a, a, e aa-e
4*3=12 1+(3*3)= 4 3 4+3=7
10
4*3=12 1+(3*3)= 4 3 4+3=7
10
36
Memory 30
Memory 12
M/As to 9M/As to 21
Memory
to Store to encode Fetch Execute Traffic
load a, b ab 3*3=9 1+(2*3)= 3 2 3+2=5
add a, c aa+c
7
mpy a, d aa*d
3*3=9 1+(2*3)= 3 3 3+3=6
7
sub a, e aa-e
3*3=9 1+(2*3)= 3 3 3+3=6
7
3*3=9 1+(2*3)= 3 3 3+3=6
7
36 28 12 11 23
 Memory Memory M/As to M/As to Memory
to Store to encode Fetch Execute Traffic
load b Accb 2*3=6 1+(1*3)= 2 1 2+1=3
add c AccAcc+c 4
mpy d AccAcc*d 2*3=6 1+(1*3)= 2 1 2+1=3
4
sub e AccAcc-e
2*3=6 1+(1*3)= 2 1 2+1=3
store a aAcc
4
2*3=6 1+(1*3)= 2 1 2+1=3
push b 6 44 2 1 3
push c 62*3=6 41+(1*3)= 22 11 32+1=3
4
add 3 1 1 0 1
30 20 10 5 15
push d 6 4 2 1 3
mpy 3 1 1 0 1
push e 6 4 2 1 3
sub 3 1 1 0 1
pop a 6 4 2 1 3
39 23 13 5 18
Based on Operation
•
Data Movement
•

•
Memory I\O Instructions
•

LOAD, STORE, MOV IN, OUT

•

•
Data Processing
•

•
Arithmetic Logic Instructions
•

•
Add, Sub, MUL AND, OR,
•

•
Control Instructions
•

• Conditional Un Conditional
•

•
JNZ, JZ…. Jump
References
Reference Book
• Vincent .P. Heuring, Harry F. Jordan “ Computer
System design and Architecture” Pearson, 2nd Edition,
2003.
•

• William Stallings “Computer Organization and

architecture”, Prentice Hall, 7th edition, 2006.