Introduction to the course
• Name: “Digital Systems Design”
• Instructor: Nguyen Cao Qui, Ph.D
email: ncqui@ctu.edu.vn
• Goals:
+ Students are able to implement digital circuits by using HDL
and FPGA.
+ Students are able to design, coding, testing digital system
circuits.
+ Students are able to be efficient in teamwork
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Introduction to the course
• Number of credits : 2
(theory: 20 hours ;Lab: 20 hours )
• Textbooks + References:
+ Donald E. Thomas, The Verilog Hardware Description
Language, Kluwer Academic Publishers, 2002.
+ James M. Lee, Verilog Quickstart A Practical Guide to
Simulation and Synthesis in Verilog, Kluwer Academic
Publishers, 2002.
+ http://www.asic-world.com/verilog/index.html
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Introduction to the course
• Course Evaluation:
+ Labs : 40%
+ Final Test: 60%
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VERILOG HDL
Chapter 1
Introduction
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Nguyễn Qui
Contents
• Introduction
• Design Styles
Bottom-Up Design
Top-Down Design
• Verilog Abstraction Levels
Behavioral Level
Register-Transfer Level
Gate Level
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Introduction
• Verilog is a HARDWARE DESCRIPTION
LANGUAGE (HDL).
• A hardware description language is a
language used to describe a digital system.
For example, a network switch, a microprocessor or
a memory or a simple flip-flop.
• By using a HDL, one can describe any (digital)
hardware at any level.
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Example
• D Flip-Flop
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Design Styles
• Verilog, like any other hardware description language, permits
a design in either Bottom-Up or Top-Down methodology.
• Bottom-Up Design: The traditional method of electronic
design is bottom-up. Each design is performed at the gate-
level using the standard gates. With the increasing complexity
of new designs this approach is nearly impossible to maintain.
• Top-Down Design: The desired design-style of all designers
is the top-down one. A real top-down design allows early
testing, easy change of different technologies, a structured
system design and offers many other advantages.
Most designs are a mix of both methods, implementing some
key elements of both design styles.
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Top-Down Design Approach
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Verilog Abstraction Levels
• Verilog supports designing at many
different levels of abstraction.
• Three of them are very important:
Behavioral level
Register-Transfer Level
Gate Level
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Verilog Abstraction Levels (cont.)
• Behavioral level
This level describes a system by concurrent
algorithms (Behavioral). Each algorithm itself
is sequential, that means it consists of a set
of instructions that are executed one after
the other.
Functions, Tasks and Always blocks are the
main elements.
There is no regard to the structural
realization of the design.
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Verilog Abstraction Levels (cont.)
• Register-Transfer Level
Designs using the Register-Transfer Level specify
the characteristics of a circuit by operations and
the transfer of data between the registers.
An explicit clock is used.
RTL design contains exact timing bounds.
Operations are scheduled to occur at certain
times.
Modern RTL code definition is "Any code that is
synthesizable is called RTL code".
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Verilog Abstraction Levels (cont.)
• Gate Level
Within the logic level the characteristics of a system are
described by logical links and their timing properties.
All signals are discrete signals. They can only have
definite logical values (‘0’, ‘1’, ‘X’, ‘Z’).
The usable operations are predefined logic primitives
(AND, OR, NOT etc gates).
Using gate level modeling might not be a good idea for
any level of logic design. Gate level code is generated by
tools like synthesis tools and this netlist is used for gate
level simulation and for backend.
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The End
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