System Verilog

CLASSES

ROHIT KHANNA
 Introduction

 System Verilog introduces an object-oriented class data type.

 Classes allow objects to be dynamically created, deleted,

assigned, and accessed via object handles.

 A class is a type that includes data and subroutines (functions and

tasks) that operate on that data.

 class’s data is referred to as class properties, and its subroutines

are called methods.

System Verilog Class

 Example1

class rectangle;
int lenght, width; //class properties

function int area(); //class method

return lenght * width;
endfunction

function int perimeter(); //class method

return 2*(lenght + width);
endfunction
endclass
System Verilog Class
 Example2

class person;
string name, address; //class properties
int number;

function void set_name(string user); //class method

name=user;
endfunction
endclass

System Verilog Class

 Example3

class packet;
bit [7:0] data; //class property

tast randomize(); //class method

data=$random;
endtask

task display();
$display(“data is %d”, data);
endtask
endclass
System Verilog Class
 Objects

 A class defines a data type. An object is an instance of that

class.

 An object is created by defining a handler of class type and then

calling new function which allocates memory to the object.

packet p; //p is handler to class packet

p=new(); //Object is constructed

 If objects are not created then handler points to null.

System Verilog Class

 Default Constructor

 new() is a default constructor which allocates memory and

initializes class variables for an object.

rectangle rec;
rec=new; //memory allocated to length and width

initial begin
int a, p;
rec.set_size(3, 5);
a=rec.area;
p=rec.perimeter; end
System Verilog Class
 Constructor

 User can define customized constructers by writing there own new

function inside a class.

 The new method is defined as a function with no return type.

 It is also possible to pass arguments to the constructor, which

allows run-time customization of an object.

function new (int x=0, y=0);

length=x;
width=y;
endfunction
System Verilog Class
 Example

rectangle r1, r2, r3;

class rectangle;
int a1, a3, p1;
int lenght, width;

function new(int x=1,y=1);..... initial begin

function int area(); ............. r1=new(3, 5);
function int perimeter(); .......... r2=new(4);
a1=r1.area;
endclass
p1=r2.perimeter;
Result: a1=15 p1=10 a3=r3.area; //error r3 is null
end

System Verilog Class

 Parameterized Class

class packet #(number=10, type dtype= bit);

dtype data [number];

function void randomize();

foreach(data[i]) data[i]=$random;
endfunction

function void display();

foreach(data[i]) $display(“data[%0d”]=%0d”, i, data[i]);
endfunction
endclass

System Verilog Class

 Parameterized Class

packet p1; //number=10, dtype=bit

packet p2#(20); //number=20, dtype=bit
packet p3#( , int); //number=10, dtype=int
packet p4#(30, bit [3:0]); //number=30, dtype=bit [3:0]

initial begin
p1=new(); p2=new(); p3=new(); p4=new();
p4.display;
p4.randomize;
p4.display;
end
System Verilog Class
 This

 The this keyword is used to unambiguously refer to class

properties or methods of the current instance.

 The this keyword shall only be used within non-static class

methods, otherwise an error shall be issued.
class example;
Now a is property of class as well as
int a;
argument of function new.
function new(int a);
a=a; SV will look in local scope to resolve
endfunction reference to a, which in this case is
endclass subroutine argument.
System Verilog Class
 This

 To solve this issue this keyword is used which now refers to

property a in current class instance.

class example; example x, y;

int a; initial begin
function new(int a); x=new(5);
this.a=a; y=new(3);
endfunction $display(x.a);
endclass $display(y.a);
end

System Verilog Class

 Fundamental Principles of OOP

 Encapsulation
o It’s a concept that binds together the data and functions that
manipulate the data.
o Encapsulation keeps both data and function safe from outside
world i.e. data hiding.

 Abstraction
o Abstraction is the concept of moving the focus from the details
and concrete implementation of things, to the types of things,
the operations available thus making the programming
simpler, more general.

System Verilog Class

 Fundamental Principles of OOP

 Inheritance
o New classes are created by inheriting properties and method
defined in an existing class.
o Existing class is called the base class(parent class), and the
new class is referred to as the derived class(child class).

 Polymorphism
o polymorphism means having many forms.
o A member function will cause a different function to be
executed depending on the type of object that invokes the
function.

System Verilog Class

 Inheritance

 Inheritance allows user to create classes which are derived from

other classes.

 The derived class (child class) inherits all the properties and
methods defined in base class (parent class).

 Additional properties and methods can be defined in child class.

 properties and methods defined in base class can be overridden

by redefining them in child class. This phenomenon is called as
overriding.

System Verilog Class

 Example1

class parent; class child extends parent;

int a, b; int c;
task display(); task print();
$display(“Parent Class”); $display(“Child Class”);
endtask endtask
endclass endclass

System Verilog Class

 Example1

parent p; parent p child c

child c; a=4 ; a=3 ;
initial begin b=0; b=0;
p=new; c=0;
c=new;
c.print;
Child Class
c.display;
Parent Class
c.a=3;
p.a=4;
end

System Verilog Class

 Example2

class parent; class child extends parent;

int a, b; int a;
task display(); task display();
$display(“Parent Class”); $display(“Child Class”);
endtask endtask
endclass endclass

Display method and property a is overridden in child class

System Verilog Class

 Example2

parent p;
parent p child c
child c;
a=2 ; a=7 ;
initial begin b=0; b=0;
p=new; c=0;
c=new;
c.display;
p.display; Child Class
Parent Class
c.a=7;
p.a=2;
end

System Verilog Class

 Example3

 A super keyword can be used to access properties and methods

defined in parent class from a child class.

class parent; class child extends parent;

int a; int a, b;
task display(); task display();
$display(“Parent Class”); $display(“Child Class”);
endtask super.display;
endclass $display(super.a);
endtask
endclass
System Verilog Class
 Example3

parent p;
parent p child c
child c;
a=5 ; a=6 ;
initial begin b=0;
p=new;
c=new;
p.a=5; Parent Class
Child Class
c.a=6;
Parent Class
p.display; 5
c.display;
end

System Verilog Class

 Inheritance

 Every time when child object is created, constructer of parent

(super.new) is called first implicitly.

 If a new function has been defined in parent which accepts a set

of arguments, in such a case super.new has to be explicitly
specified with required arguments.

 It is because of this reason that child class is able to access

properties and methods defined in parent class.

System Verilog Class

 Example4

class parent; class child extends parent;

function new(); function new();
$display(“Parent Class”); $display(“Child Class”);
endfunction endfunction
endclass endclass

initial begin
Parent Class
child c;
Child Class
c=new;
end

System Verilog Class

 Example5

class parent; class child extends parent;

function new(string str); function new();
$display(str); $display(“Child Class”);
endfunction endfunction
endclass endclass

initial begin
child c;
Error super.new is not called
c=new;
end

System Verilog Class

 Example6

class parent; class child extends parent;

function new(string str); function new();
$display(str); super.new(“Parent Class”);
endfunction $display(“Child Class”);
endclass endfunction
endclass
initial begin
child c; Parent Class
c=new; Child Class
end

System Verilog Class

 Example7

class rectangle; class square extends rectangle;

int length, width; int size;
function new(int size);
function new(int x, y); this.size=size;
this.length=x; super.new(size, size);
this.width=y; endfunction
endfunction endclass
function int area(int x, y);....
function int perimeter(int x, y);... square sq= new(5);
sq.area;
endclass sq.perimeter;

System Verilog Class

 Encapsulation

 Till now classes have members which were accessible to rest of

the program. However in many situation such functionality are
not desired.

 Example: In cars we are not concerned by how engine works but

we our focus is how to control it.

 System Verilog provides various ways of hiding class members:

o local keyword will ensure that the members are available
only to the method of the same class.
o protected keyword is similar to local keyword but members
can also be accessed by child class.

System Verilog Class

 Example1

class rectangle; rectangle rec;

int length, width;
initial begin
function new(int x, y); rec=new(2, 3);
this.length=x; rec.area;
this.width=y; rec.length=5; //length is modified
endfunction rec.area;

function int area; ….

end
endclass

System Verilog Class

 Example2

class rectangle; rectangle rec;

local int length, width;
initial begin
function new(int x, y); rec=new(2, 3);
this.length=x; rec.area;
this.width=y; rec.length=5; //error
endfunction rec.area;

function int area; ….

end
endclass

System Verilog Class

 Example3

class rectangle; class square extends rectangle;

local int length, width; function new (int x);
function new(int x, y); super.new(x, x);
this.length=x; endfunction
this.width=y; endclass
endfunction
square sq;
function int area; …. initial sq=new(3);
endclass Error length and width are local to class rectangle

System Verilog Class

 Example4

class rectangle; class square extends rectangle;

protected int length, width; function new (int x);
length=x;
function new(int x, y);
width=x;
this.length=x;
endfunction
this.width=y;
endclass
endfunction
square sq;
function int area; ….
initial sq=new(3);
endclass
Now length and width are accessible to both rectangle and square
System Verilog Class
 Lifetime in Class

 By default properties and methods defined inside a class have

automatic lifetime.

 Memory to properties are allocated dynamically when a new

instance of the class is created.

 User can define properties and methods as static. A static

property is a class variable that is associated with the class,
rather than an instance of the class.

System Verilog Class

 Lifetime in Class

 Memory to static properties and methods are allocated during

elaboration time.

 Scope resolution operator ( :: ) can be used to access static

property and methods defined inside a class.

 Static properties and methods can be accessed without creating

any instance of a class.

System Verilog Class

 Example1

packet p1, p2, p3;

class packet;
static int id; initial begin
int val; //default: automatic p1=new; $display(p1.id, p1.val);
p2=new; $display(p2.id, p2.val);
function new();
p3=new; $display(p3.id, p3.val);
id++;
p2.id=7; p2.val=3;
val++;
$display(p1.id, p1.val);
endfunction
$display(p2.id, p2.val);
endclass $display(packet :: id);
end
System Verilog Class
 Example1

Result :
p1.id= 1 p1.val=1
p2.id= 2 p2.val=1
p3.id= 3 p3.val=1
p1.id= 7 p1.val=1
p2.id= 7 p2.val=3
packet :: 7

System Verilog Class

 Example2

initial begin
class packet;
packet:: id=3;
static int id;
$display(packet::id);
int val; //default: automatic
packet p1;
function new(); p1=new;
id=id++; $display(packet::id);
val=++val; end
endfunction
Result
endclass id=3; id=4;

System Verilog Class

 Functions and Tasks

 Task and Functions defined inside class have automatic lifetime

for their arguments and variables.

 A static keyword can be added after Task/Function to make

arguments and variables static in nature.

 A function prototype can be declared inside a class and body

can be defined outside class with help of extern keyword.

System Verilog Class

 Example1

class test;
initial begin
task increment; test t1;
Result:
int i; t1=new;
i=1
i++; t1.increment;
i=1
$display(“i=%d”, i); t1.increment;
i=1
endtask t1.increment;
end
endclass

System Verilog Class

 Example2

class test;
initial begin
task increment;
test t1;
static int x; Result:
t1=new;
int y; x=1 y=1
t1.increment;
x++; y++; x=2 y=1
t1.increment;
$display(“x=%d y=%d”, x, y); x=3 y=1
t1.increment;
endtask
end
endclass

System Verilog Class

 Example3

class test;

task static increment; initial begin

int x; test t1; Result:
int y; t1=new; x=1 y=1
x++; y++; t1.increment; x=2 y=2
$display(“x=%d y=%d”, x, y); t1.increment; x=3 y=3
endtask t1.increment;
end
endclass

System Verilog Class

 Example4

class test;
initial begin
task static increment;
test t1; Result:
int x;
t1=new; x=1 y=1
automatic int y;
t1.increment; x=2 y=1
x++; y++;
t1.increment; x=3 y=1
$display(“x=%d y=%d”, x, y);
t1.increment;
endtask
end
endclass

System Verilog Class

 Example5

function rectangle :: new(int x, y);

class rectangle; this.length=x;
local int length, width; this.widht=y;
extern function new(int x, y); endfunction
extern function int area();
function int rectangle::area();
endclass
return length*width;
endfunction

System Verilog Class

 Functions and Tasks

 Functions and Tasks can be local as well as protected.

 Functions and Tasks can also be declared as static. The lifetime

of variables inside static methods are automatic by default.

 Memory to static methods are allocated during elaboration time.

 A static methods can only access static members of a class.

 A static method can be called without creating instance of a

class. They can be accessed by scope resolution operator(::).

System Verilog Class

 Example1

class test;
int i; initial begin
local function void increment; test t1;
Result:
i++; $display(“i=%0d”, i); t1=new;
i=1
endtask t1.inc;
i=2
t1.inc;
function void inc;
//t1.increment; will give
increment;
//compilation error
endfunction
end
endclass
System Verilog Class
 Example2

class test;
initial begin
static function int add(int x, y); $display(test::add(3,2));
int i; $display(test::add(1,1));
i++; end
$display(“i=%0d”, i);
return x + y; Result:
endfunction 5 i=1
2 i=1
endclass

System Verilog Class

 Example3

class test;
initial begin
int i;
$display(test::add(3,2));
static function int add(int x, y); $display(test::add(1,1));
i++; end
$display(“i=%0d”, i);
return x + y;
endfunction Result :
Error, Static function cannot access non-
endclass static class properties

System Verilog Class

 Example4

class test;
initial begin
static int i;
$display(test::add(3,2));
static function int add(int x, y); $display(test::add(1,1));
i++; end
$display(“i=%0d”, i);
return x + y; Result:
endfunction 5 i=1
2 i=2
endclass

System Verilog Class

 Polymorphism

 Polymorphism is an ability to appear in many forms.

 In OOPS multiple routines sharing a common name is termed as

Polymorphism.

 In SV, Polymorphism allows a parent class handler to hold sub

class object and access the methods of those child classes from
the parent class handler.

 To achieve this, functions/tasks in SV are declared as virtual

functions/tasks which allow child classes to override the
behaviour of the function/task.

System Verilog Class

 Example1

class shape; //Main Class

protected x, y, z;
virtual function void display(); //Function call can be
$display(“I am shape”); // overridden, will call
endfunction //child function instead

virtual function void perimeter();

$display(“I don’t know perimeter”);
endfunction

endclass

System Verilog Class

 Example1

class rectangle extends shape;

virtual function void display();
$display(“I am rectangle”);
endfunction

virtual function void perimeter();

$display(“perimeter=%0d”, 2*(x + y));
endfunction
function new (int x, y); .....
endclass

System Verilog Class

 Example1

class square extends rectangle;

function void display(); //This function call
$display(“I am square”); //cannot be overridden
endfunction

function void perimeter();

$display(“perimeter=%0d”, 4*x);
endfunction
function new (int x); .....
endclass

System Verilog Class

 Example1

class triangle extends shape;

function void display();
$display(“I am a triangle”);
endfunction

function void perimeter();

$display(“perimeter=%0d”, (x + y + z));
endfunction
function new (int x, y, z); .....
endclass

System Verilog Class

 Example1

shape s1, s2;

s1.display; s1.perimeter;
rectangle r1,r2;
r1.display; r1.perimeter;
square sq1;
t1.display; t1.perimeter;
triangle t1;
s2=t1;
s2.display; s2. perimeter;
initial begin
r2=sq1;
s1=new;
r2.display; r2. perimeter;
r1=new(2, 3);
s2=r1;
sq1=new(4);
s2.display; s2. perimeter; end
t1=new(1, 2, 3);

System Verilog Class

 Example1

Result :
I am shape I don’t know perimeter
I am rectangle Perimeter= 10
I am triangle Perimeter= 6
I am triangle Perimeter= 6
I am square Perimeter= 16
I am rectangle Perimeter= 10

System Verilog Class

 Example2

class parent; class child extends parent;

int a=3; int a=5, b=8;

function void d1(); function void d1();

$display(“Parent d1”); $display(“Child d1”);
endfunction endfunction

virtual function void d2(); function void d2();

$display(“Parent d2”); $display(“Child d2”);
endfunction endfunction
endclass endclass

System Verilog Class

 Example2

initial begin
parent p1; child c1;
c1=new;
$cast(p1, c1); // checks run-time casting errors
//p1=c1; //checks compile time casting errors
//Properties and virtual methods in parent class points to one
//defined in child class
p1.d1; p1.d2;
$display(“p1.a=%0d”, p1.a); c1.a=9;
$display(“p1.a=%0d”, p1.a);
end
System Verilog Class
 Example2

parent p child c parent p child c

a; a; after p1=c1; d1 ; b;
d1 ; b; d1;
d2; d1; d2;
Shared
Result : Memory
Parent d1 a;
d2;
Child d2
p1.a=5 parent points to child memory for
p1.a=9 same properties and virtual methods

System Verilog Class

 Abstraction

 Sometimes, it is useful to create a class without intending to

create any objects of the class.

 The class exists simply as a base class from which other classes
can be derived.

 In System Verilog this is called an abstract class and is declared

by using the word virtual.

 A virtual class object can not be constructed but handle to the

virtual class can be defined.

System Verilog Class

 Abstraction

 Virtual methods can be declared without any body.

 These methods can be overridden in a derived class.

 The method overriding virtual method should have same

signature i.e. (return type, number and type of arguments) must
be the same as that of the virtual method.

 If a virtual method is defined as pure then these methods must

be defined in child classes. A pure virtual method forces child
classes to implement standard set of methods.

System Verilog Class

 Example1

virtual class abstract; //Abstract Class

virtual task display(); //Virtual Method

endtask //Body not defined

function int increment(int x);

return x + 1;
endfunction
endclass

System Verilog Class

 Example1

class abc extends abstract;

task display(); // display may or may not be defined

$display(“abc”);
endtask

function int increment(int x); //Overriding

return x + 2;
endfunction

endclass

System Verilog Class

 Example1

class xyz extends abstract;

task display(); // display may or may not be defined

$display(“xyz”);
endtask

//Increment function may not be defined

endclass

System Verilog Class

 Example1

abstract ab; initial begin

abc a; //ab=new; not allowed
xyz x; //will give compilation error
a=new; x=new;
int p1, p2; a.display; x.display;
Results: p1=a.increment(3);
abc xyz p2=x.increment(4);
4 6 ab=x; ab.display;
xyz abc ab=a; ab.display;
end

System Verilog Class

 Example2

virtual class abstract; //Abstract Class

pure virtual task display();

//Pure Virtual Method

virtual function int increment(int x); //Virtual Function

endfunction //Body may not be defined

endclass

System Verilog Class

 Example2

class abc extends abstract;

task display(); //display method needs to be defined

$display(“abc”); //will give compilation error if not defined
endtask

function int increment(int x); //Increment function may

return x + 2; // or may not be defined
endfunction

endclass

System Verilog Class

 Nested Class

 A class can contain instance of another class using handle to an

object. Such classes are called as Nested Classes.

 Common reasons for using containment are reuse and controlling

complexity.

class Node;
Node left, right;
//properties and methods for Node
endclass

System Verilog Class

 Example

class timestat;
time start_time, end_time;

function void start;

start_time=$time;
endfunction

function void end;

end_time=$time;
endfunction
endclass

System Verilog Class

 Example

class packet;
int data[7:0];
task packet :: transmit();
timestat t;
t.start;
function new; //do some operation
t=new; t.end;
endfunction endtask

extern task transmit;

endclass

System Verilog Class

 Typedef Class

 A forward declaration is a declaration of a object which the

programmer has not yet given a complete definition.

 System Verilog language supports the typedef class construct

for forward referencing of a class declaration.

 This allows for the compiler to read a file from beginning to end
without concern for the positioning of the class declaration.

System Verilog Class

 Example

module test;
class packet;
timestat t; Compilation error class
//definitions timestat is not defined.
endclass

class timestat; Timestat is referred before

//definitions it is defined
enclass
endmodule

System Verilog Class

 Example

module test;
typedef class timestat;
class packet;
timestat t; typedef allows compiler to
//definitions process packet class before
endclass timestat class.

class timestat;
//definitions
enclass
endmodule
System Verilog Class
 Copy

 User can make a copy of an object to keep a routine from

modifying the original.

 There are two ways of copying an object:

o Using built-in copy with new function (Shallow Copy)
o Writing your own complex copy function (Deep Copy)

 Using new to copy an object is easy and reliable. A new object

is constructed and all variables from the existing object are
copied.

System Verilog Class

 Shallow Copy

class pkt; pkt src, dst;

bit addr [15:0]; initial begin
bit [7:0] data; src=new; //create object
int status; dst=new src; //copy to dst
end
function new();
addr=$randomize;
data=$randomize; src dst
status=0; addr=5 ; addr=5 ;
endfunction data=10; data=10;
endclass status=0; status=0;

System Verilog Class

 Shallow Copy

 Shallow copy is similar to photocopy, blindly copying values from

source to destination.

 If a class contains handle to another class then only top level

objects are copied by new, not the lower one.

 When using new to copy objects, the user define new constructer
is not called. New function just copies the value of variables and
object handle.

System Verilog Class

 Example

class pkt;
bit addr [15:0];
class timestat;
bit [7:0] data;
time start_time, end_time; int id; static int count;
endclass timestat t;

function new();
id=count++;
t=new;
endfunction
endclass

System Verilog Class

 Example

packet src, dst;

initial begin
src=new; src dst
src.t.start_time=10; id=1 ; id=1 ;
dst=new src;
//handle of t is copied
//id is not incremented t
start_time=14 ;
dst.t.start_time=14;
//modifies t since
// handler is common
end
System Verilog Class
 Deep Copy

 User can write his own deep copy function.

 This user defined copy function should copy the content of class
handle, not handle itself.

System Verilog Class

 Example

class pkt;
bit addr [15:0];
bit [7:0] data;
int id; static int count; function pkt pkt :: copy;
copy=new;
timestat t; copy.addr=this.addr;
copy.data=this.data;
function new(); endfunction
id=count++;
t=new;
endfunction
extern function pkt copy;
endclass
System Verilog Class
 Example

initial begin src dst

pkt src, dst; id=1 ; id=2 ;
src=new;
src.t.start_time=3;
dst=src.copy;
dst.t.start_time=7; t t
end start_time=3 ; start_time=7 ;

System Verilog Class

 Interface Class

 A set of classes can be created that have a common set of

behaviors. This set is called Interface class.

 An interface class can only contain pure virtual functions, type

declaration and Parameter declarations.

 Pure functions are function that don’t have any implementation.

 implements keyword is used to define a class that implements

function defined in interface class.

 When interface class is implemented then nothing is extended,

implementation of pure virtual function is defined in class that
implements interface class.
System Verilog Class
 Interface Class

interface class shape #(type id=int);

int a;
pure virtual function id area(id x=0, y=0);
pure virtual function id perimeter(id x=0, y=0);
endclass

System Verilog Class

 Interface Class

class int_rectangle implements shape #(int);

virtual function int area(int x=0, y=0); //virtual keyword

return x*y; //compulsory
endfunction

virtual function int perimeter(int x=0, y=0);

return 2*(x+y);
endfunction
//a defined in interface class cannot be accessed
endclass

System Verilog Class

 Interface Class

class real_rectangle implements shape #(real);

virtual function real area(real x=0, y=0);

return x*y;
endfunction

virtual function real perimeter(real x=0, y=0);

return 2*(x+y);
endfunction

endclass

System Verilog Class

 Singleton Class

 These are classes that restricts instantiation of class to just one

object.

class singleton; static function singleton create(int a);

int a; if (obj==null)
static singleton obj; obj=new(a);
return obj;
local function new (int a);
endfunction
this.a=a;
endfunction
initial begin
//static function singleton s1;
s1=singleton::create();
endclass end
System Verilog Class
 Semaphore

 Semaphore is a built-in class which conceptually is a bucket.

 When semaphore is allocated, then a bucket containing fixed

number of keys is created.

 Process using semaphore must first procure a key from bucket

before they can continue to execute.

 Once process is over, key should be returned back to the bucket.

 Semaphore is basically used to control access to shared resources.

System Verilog Class

 Semaphore - Methods

 new() method is used to create semaphore with specified number

of keys. Default key count is 0.

 put() method is used to return specified number of keys to

semaphore. Default value is 1.

 get() method is used to procure specified number of keys from

semaphore. Default value is 1.

System Verilog Class

 Semaphore - Methods

 In get() method if the specified number of keys is not available,

the process blocks until the keys become available.

 try_get() method is used to procure a specified number of keys

from a semaphore, but without blocking.

 In try_get() method if the specified number of keys are not

available, the method returns 0 else a positive value and
continues.

System Verilog Class

 Example

semaphore smp;
int got=0;
initial
initial begin begin
smp=new(5); #8 smp.get(2);
#5 smp.get(3); #7 smp.put(2);
#6 smp.get(1); got=got +1; end
#2 if(smp.try_get(3)) got=got +1; got=1 at 15
end

System Verilog Class

 Example

module test; begin : statement1

semaphore smp; smp.get;
int a=0; a=7;
smp=new(1); #3 smp.put;
end statement1
initial
fork begin : statement2
//statement1 smp.get;
//statement2 a=3;
join #2 smp.put;
end statement2
System Verilog Class
 Mailbox

 Mailbox is a built-in class that allows messages to be exchanged

between processes.

 Data can be sent to mailbox by one process and retrieved by

another.

 Mailbox can be bounded or unbounded queues.

 Mailbox can be parameterized or Non-parameterized.

 Non-Parameterized mailboxes are typeless , that is single

mailbox can send and receive different type of data.

System Verilog Class

 Mailbox - Methods

 new() method is used to create mailbox with size specified as an

argument.

 If size is defined as 0 (default) then mailbox is unbound.

 num() method is returns the number of message currently present

inside mailbox.

 put() method places a message in a mailbox in a FIFO order.

 If the mailbox is bounded, the process shall be suspended until

there is enough room in the queue.

System Verilog Class

 Mailbox - Methods

 try_put() method attempts to place a message in mailbox. This

method is meaningful only for bounded mailboxes.

 If mailbox is full this method returns 0 and message is not placed

else it returns 1 and message is placed.

 get() method retrieves a message from a mailbox.

 This method removes message from a mailbox and calling process

is blocked if mailbox is empty.

 try_get() method attempts to retrieves a message from a mailbox

without blocking.

System Verilog Class

 Mailbox - Methods

 peek() method copies message from a mailbox without removing

message from the queue.

 If mailbox is empty then current process is blocked till a message

is placed in the mailbox.

 If the type of the message variable is not equivalent to the type

of the message in the mailbox, a run-time error is generated.

 try_peek() method attempts to copy a message from a mailbox

without blocking. If the mailbox is empty, then the method returns
0 else if variable type is different it returns negative number else
positive number is returned.
System Verilog Class
 Parameterized Mailboxes

 By default mailboxes are typeless. They can send and receive

different data types. This may lead to runtime errors.

 Mailbox type can be parameterized by passing type as a

argument.
mailbox #(string) mbox;

 In parameterized mailboxes, tools catches type mismatch errors

at compilation time.

System Verilog Class

 Example

module test;
mailbox mb; //typeless Mailbox

string s, int i;
initial begin
mb=new(); //Unbound Mailbox
$monitor(“s=%s and i=%0d at time=%0d”, s, i, $time);
fork gen_data;
rec_data;
join end
endmodule
System Verilog Class
 Example

task rec_data;
task gen_data;
#1 mb.peek(s);
mb.put(“Hello”);
#2 mb.get(s);
#3 mb.put(7);
#2 mb.get(i);
#4 mb.put(“Test”);
#1 mb.peek(s);
#3 mb.put(3);
#2 void’( mb.try_get(s));
#3 mb.put(“Hi”);
#1 void’(mb.try_get(i));
#2 mb.put(9);
#4 mb.get(s);
endtask
#2 mb.get(i);
endtask

System Verilog Class

 Example

Result:
# s= and i=0 at time=0
# s=Hello and i=0 at time=1
# s=Hello and i=7 at time=5
# s=Test and i=7 at time=7
# s=Test and i=3 at time=16

System Verilog Class

 Example

module test;
mailbox #(int) mb; //Parameterized Mailbox

int i;
initial begin
mb=new(3); //bound mailbox
$monitor(“i=%0d at %0d”, i ,$time);
fork gen_data;
rec_data;
join end
endmodule
System Verilog Class
 Example

task gen_data; task rec_data;

mb.put(1); #1 mb.peek(i);
#1 mb.put(7); #5 mb.get(i);
#1 mb.put(4); #2 mb.get(i);
#2 mb.put(3); #2 void’(mb.try_get(i));
#2 void’(mb.try_put(2)); #1 mb.get(i);
#10 mb.put(5); #2 void’(mb.try_get(i));
#2 mb.put(6); #2 void’(mb.try_peek(i));
endtask #2 mb.get(i);
endtask
System Verilog Class
 Example

Result:
# i=0 at time=0
# i=1 at time=1
# i=7 at time=8
# i=4 at time=10
# i=3 at time=11
# i=2 at time=13
# i=5 at time=17

System Verilog Class