LAB INDEX
Student Name ______________________ Branch_________ Sem___________Year_______
SN Session Title Pages Marks Signature
(MM-100)
I Introduction to Lab, Objectives & Outcomes
Intro to Low Level Programming - I – Write an
1. assembly program to add numbers stored in two of 10
registers and store the result in third register.
Intro to Low Level Programming - II – Write an
2. assembly program to find the greatest of three of 10
numbers stored in registers.
Intro to Low Level Programming - III – Write
3. an assembly program to find the number of ones in of 10
a binary 8-bit number.
Review of Combinational & Sequential Circuits
4. – Design a ripple carry adder/subtractor circuit of 10
that takes input from PIPO registers.
Designing ALU & Shift Unit – Part I – Design
5. circuits for a 4-bit adder, 4-bit AND logic, 4-bit of 10
NOT Logic and 4-bit shift logic.
Designing ALU & Shift Unit – Part II –
6. Integrate all ALU and shift units using multiplexed of 10
logic, identify all inputs and outputs.
Designing Random Access Memory – Design
7. circuit to implement a random access memory incl. of 10
MBR & MAR Registers and other control signals.
Designing a Multiplexed Bus – Establish data
8. paths between GPRs, PC, IR, memory and ALU of 10
using a multiplexed common bus.
Designing an Instruction Decoder – Design
instruction set and circuit for an instruction
9. of 10
decoder based on ALU and memory designed
earlier.
Executing Instructions – Implement fetch, decode
10. and execute cycle for executing instruction stored of 10
in memory.
(Optional) Writing Machine Level Programs –
Write machine level programs equivalent to the
11.
assembly programs written in first three
experiments.
Submission Date with
SN Session Title
no penalty
1. Intro to Low Level Programming - I
2. Intro to Low Level Programming - II April 27, 2019
3. Intro to Low Level Programming - III
4. Review of Combinational & Sequential Circuits
5. Designing ALU & Shift Unit – Part I May 01, 2019
6. Designing ALU & Shift Unit – Part II
7. Designing Random Access Memory
May 11, 2019
8. Designing a Multiplexed Bus
9. Designing an Instruction Decoder
May 20, 2019
10. Executing Instructions
11. Writing Machine Level Programs No Deadline (Optional)
1. Each assignment documented in file must have four sections – Objective, Approach, Circuit
Diagram (Screenshot), Test Output (as shown in screenshot).
2. Every three days after the above submission dates will invite 2 marks deduction for each
delayed assignment.
3. If you have completed the assignments before the due date and could not get your
assignments checked due to any reason, write me a mail stating your reason and attach the
required file with it. In absence of such a formal request, you will invite the mentioned
deductions despite of any genuine reason for non-submission.
4. No assignment will be checked beyond two weeks from the due date.
