Sequential logic
Asynchronous sequential logic – state changes occur
whenever state inputs change (elements may be simple wires
or delay elements)
Synchronous sequential logic – state changes occur in lock
step across all storage elements (using a clock signal – a
periodic waveform)
Clock
Basis of sequential circuits: the R-S latch
Cross-coupled NOR gates R
Q
Q
R Q
S
S
can force output to 0 (reset) or 1 (set)
fundamental component of ALL latches and flip-flops
0 1
D’ 0
D D
1
0
Q
Q
0
Two stable states when R=S=0
R R
Q Q
Q Q
S S
R
Q
Q
S
S changes 0⇒1
R
Q
Q
S
2
R
Q
Q
S
R changes 0⇒1
R
Q
Q
S
R
Q
Q
S
S and R =1
R
Q
Inconsistent
values
Q
S
3
R
Q
Q
S
S and R change 1⇒0
R
Q
Q
S
Summary: the R-S latch
R
Q
Q
R
S Q
S
Timing waveform
Reset Hold Set Force Race
R
S
Q
Q
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Gated R-S Latch
R
Q
CLK
Q
S
CLK
operates as R-S latch holds value
R and S better not
both be 1 here
Gated D Latch D Q
CLK
D R
Q
CLK
\Q
S
Clk D Q(t+1)
0 -- Q(t)
1 0 0
1 1 1
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Latches vs Flip-Flops
D Q
Q latch
CLK
transparent D
(level-sensitive)
latch Clk
D Q Q edge
positive
edge-triggered
flip-flop
behavior is the same unless input changes
while the clock is high
Master Slave Flip-Flops D Q
M
D D Q D Q Q
CLK CLK
Clk
Clk
D
M
Clk
Q
Negative edge-triggered Flip-Flop
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A Smaller Negative edge-triggered flip-flop
D Q
Sensitive to inputs only near edge of clock signal
4-5 gate delays
Characteristic equation: Q(t+1) = D(t)
Setup and hold times necessary to successfully latch the input
holds D when
holds D when
clock goes low
clock goes low
Clk = 1 0
0
S
D’ R Q
Q
D Q D
S
0 R
Q
Q
Analysis of negative edge-triggered flip-flop
Clk == 10
Clk DQ
D’
S
D’ R
Q
Q
D \Q D D’
D’
S
R
Q D
Q
When Clk=0 two stable states
Clk
Clk == 01 Q Clk
Clk == 01 Q
D’ D’
newD
D D
newD
Q Q
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Analysis of negative edge-triggered flip-flop
Hold or setup time violation:
D changes before the effects of the clock edge have
propagated through flip-flop
Clk
Clk == 01 Q
S Q
Q
Q
D
Q
R
S Q
Q
Clocking Requirements
clock: periodic event, causes state of memory element to change
can be rising edge or falling edge or high level or low level
setup time: minimum time before the clocking event by which the
input must be stable ( Tsu )
hold time: minimum time after the clocking event until which the
input must remain stable ( Th )
input Tsu Th
data
D Q D Q
clock
clock
there is a timing "window" around
the clocking event during which the stable changing
input must remain stable and data
unchanged in order to be recognized
clock
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Typical timing specifications
Positive edge-triggered D flip-flop
setup and hold times
minimum clock width
propagation delays (low to high, high to low, max and typical)
T su T h
T su T h
20ns 5ns 20ns 5ns
Clock T
w T
w
25ns 25ns
Q
30ns 20ns
Tplh Tphl
All measurements are made from the clocking event
In this case, the rising edge of the clock
Cascaded Flip-Flops
IN Q0 D1 Q1
D Q D Q
C Q C Q
CLK
shift register:
new value to first stage while second stage
obtains current value of first stage
Clk
IN
Q0
Q1
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Cascaded Flip-Flops (continued)
Setup/hold/propagation delays must be balanced
Works when: propagation delays far exceed hold times
clock period exceeds setup time
(guarantees following stage will latch current value
before it is replaced by new value)
Clk
IN Tsu T Tsu
plh
Q0
Th Th
D1
Tplh
Q1 Tphl
assuming perfect clock distribution !!!
Timing problems
Setup time violations
must lengthen clock period or speedup signal, get faster logic
Hold time violations
slow down signal, slower logic
Clock skew
shifts relative time clock edge arrives at FFs
may lengthen setup and hold time requirements
Asynchronous signals
real world interfaces - real world isn't controlled by the same clock
interfaces to other systems with different clocks
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Clock skew
Ideally – all storage elements clocked at the same time
Reality -- different wire delay to different points in the
circuit causes skew between clock inputs
Effect of skew on cascaded flip-flops:
Clk
IN
Q0
D1
Clk2
Q1
Clock skew
Can shorten time available for logic propagation
Tsu Tsu
Clk
Tp Tp
Tsu
Clk2
Time for logic
to propagate
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Strategies for minimizing clock skew
Distribute clock signals in general direction of data flow
Wires carrying clock between communicating components
should be as short as possible
Make all wires from the clock source the same length
When skew is of same order as FF propagation
delays, problems arise.
Worsens as systems get faster (wire delays don't
improve as fast as circuit delays).
Metastability and asynchronous inputs
Clocked synchronous circuits
Inputs, state, and outputs sampled or changed in relation to a
common reference signal (called the clock)
Asynchronous circuits
Inputs, state, and outputs sampled or changed independently of a
common reference signal (glitches/hazards a major concern)
(e.g., R-S latch)
Asynchronous inputs to synchronous circuits
Inputs can change at any time, will not meet setup/hold times
Dangerous, synchronous inputs are greatly preferred
Unavoidable (e.g., reset signal, memory wait, user input)
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Handling asynchronous inputs
Never allow asynchronous inputs to be fanned out to more
than one FF
Different FFs could decide differently and the result could be
and incorrect or illegal state
Clocked
Synchronous Q1
System
Async
Input D Q
Q0 Q0
In
Clock
Clk Q1
D Q
Synchronizer
Clock
Async Q0
Input D Q D Q
Clock
Q1
D Q
adds delay to input into system Clock
Synchronizer failure
When FF input changes near clock edge, the FF may enter a metastable
state – neither a logic 0 nor 1 – it may stay in this state an indefinite
amount of time, although this is not likely in real circuits.
small, but non-zero probability that oscilloscope traces demonstrating
FF output will get stuck in an synchronizer failure and eventual
in-between state
decay to steady state
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Solutions to synchronizer failure
Slow down the system clock
to give synchronizer more time to decay into steady state
Use fastest possible logic in the synchronizer
this makes for a very sharp "peak" upon which to balance
Cascade two synchronizers
Q synchronized
asynchronous D Q D Q
input input
Clk
Probability of failure can never be made 0, but it
can be substantially reduced
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