CSE – 4th Semester
COMPUTER ARCHITECTURE
& ORGANIZATION
Introduction to Sequential
Circuits
Inputs Outputs
Combina-
A Sequential
circuit contains: tional
Storage
Storage elements: Logic
Latches or Flip-Flops
Elements
Combinational Logic: Next
Implements a multiple-output State State
switching function
Inputs are signals from the outside.
Outputs are signals to the outside.
Other inputs, State or Present State,
are signals from storage elements.
The remaining outputs, Next State
are inputs to storage elements.
The Sequential Circuit Model
x1 z1
C o m b in atio n al
xn lo g ic zm
(a)
x1 z1
xn C o m b in atio n al zm
lo g ic
y1 yr Yr Y1
M em o ry
(b )
Figure 6.1
Types of Sequential Circuits
Depends on the times at which:
storage elements observe their inputs, and
storage elements change their state
Synchronous or clocked
Storage elements observe inputs and can
change state only in relation to a timing
signal (clock pulses from a clock). In this
we use a master oscillator which provide
regular timing pulse.
Asynchronous or unclocked
In this the circuit events can occur after
one event is completed and there is no
waiting for the timing pulse.
Flip-Flops
The memory elements used in clocked type
sequential circuits are called Flip-Flops.
Flip-Flops are also known as bistable multi-
vibrators, latches, multibinary and toggles.
Flip-flops are inter connected to form
sequential logic circuits, such as storage
circuits, counters, shift registers and in
various other computer applications.
Basic (NOR) S – R Latch
Cross-coupling two R (reset)
NOR gates gives the Q
S – R Latch:
Which has the time
sequence behavior:
S (set) Q
Time R S Q Q Comment
0 0 ? ? Stored state unknown
0 1 1 0 “Set” Q to 1
0 0 1 0 Now Q “remembers” 1
1 0 0 1 “Reset” Q to 0
0 0 0 1 Now Q “remembers” 0
1 1 0 0 Both go low
0 0 ? ? Unstable!
Clocked S - R Latch
Adding two NAND S
gates to the basic Q
S - R NAND latch
gives the clocked
S – R latch:
C
Q
R
Has a time sequence behavior similar to the basic S-R latch
except that the S and R inputs are only observed when the line
C is high.
C means “control” or “clock”.
Clocked S - R Latch (continued)
The Clocked S-R Latch can be described by a table:
S
Q(t) S R Q(t+1) Comment
Q 0 0 0 0 No change
C 0 0 1 0 Clear Q
0 1 0 1 Set Q
Q
R 0 1 1 ??? Indeterminate
1 0 0 1 No change
The table describes
1 0 1 0 Clear Q
what happens after the 1 1 0 1 Set Q
clock [at time (t+1)]
1 1 1 ??? Indeterminate
based on:
current inputs (S,R) and
current state Q(t).
D Latch
D
Adding an inverter Q
to the S-R Latch,
gives the D Latch: C
Note that there are
no “indeterminate” Q
states!
The graphic symbol for a
Q D Q(t+1) Comment D Latch is:
0 0 0 No change D Q
0 1 1 Set Q
1 0 0 Clear Q
C Q
1 1 1 No Change
S-R Master-Slave Flip-Flop
Consists of two clocked
S S Q S Q
S-R latches in series Q
with the clock on the C C C
second latch inverted R R Q R Q Q
The input is observed
by the first latch with C = 1
The output is changed by the second latch with C = 0
The path from input to output is broken by the difference in
clocking values (C = 1 and C = 0).
The behavior demonstrated by the example with D driven by Y
given previously is prevented since the clock must change
from 1 to 0 before a change in Y based on D can occur.
Flip-Flop Problem
The change in the flip-flop output is delayed by the pulse
width which makes the circuit slower or
S and/or R are permitted to change while C = 1
Suppose Q = 0 and S goes to 1 and then back to 0 with R
remaining at 0
The master latch sets to 1
A 1 is transferred to the slave
Suppose Q = 0 and S goes to 1 and back to 0 and R goes
to 1 and back to 0
The master latch sets and then resets
A 0 is transferred to the slave
This behavior is called 1s catching
Flip-Flop Solution
Use edge-triggering instead of master-slave
An edge-triggered flip-flop ignores the pulse while it is
at a constant level and triggers only during a
transition of the clock signal
Edge-triggered flip-flops can be built directly at the
electronic circuit level, or
A master-slave D flip-flop which also exhibits edge-
triggered behavior can be used.
Edge-Triggered D Flip-Flop
The edge-triggered D D S
Q Q Q
D flip-flop is the
same as the master- C
slave D flip-flop C C Q R Q Q
It can be formed by:
Replacing the first clocked S-R latch with a clocked D latch or
Adding a D input and inverter to a master-slave S-R flip-flop
The delay of the S-R master-slave flip-flop can be avoided since
the 1s-catching behavior is not present with D replacing S and R
inputs
The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
It is called a negative-edge triggered flip-flop
Counters
14
Counters
Counters are one of the important digital
electronic circuits used to count the occurrence
of the event, or generating timing sequence to
control operation in digital system. For e.g
digital clock.
Counter circuits produces a well-defined output
pattern sequence like:
3 Bit Up-counter: 000, 001, 010, 011, 100, 101,
110, 111, 000, ...
3 Bit Down-counter: 111, 110, 101, 100, 011,
010, 001, 000, 111, ...
Binary vs. BCD vs. Gray Code
The output pattern = state of the counter
Total number of states = modulus of counter
Counter with m states = modulus-m counter
or mod-m counter
Asynchronous Binary Counters
Binary counters = counters whose counting
sequence corresponds to binary numbers
Modulus of a binary counter is 2n, where n is
numer of flip-flops
Also known as ripple counter since a change
in Qi flip-flop toggles the Qi+1 flip-flop
3-bit Asynchronous Up-Counter
4-bit(Asynchronous) Ripple Counter
Q3 Q2 Q1 Q0 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1 Q1
0 1 0 0
0 1 0 1
0 1 1 0 Q2
0 1 1 1
1 0 0 0
Q3
Synchronous Counters
All FFs are triggered simultaneously (in parallel) by
clock input pulses.
All outputs change simultaneously
Simple counters use TFF or JKFF
JK inputs of the others FFs are driven by some
combination of FF outputs.
Synchronous Counter
Serial enable logic
Shift Registers
22
(Shift) Registers
Registers are used for storage and transfer of binary
information in a digital system.
The storage capacity of a register is defied as a
number of bits of digital data it can store or retain.
Types
Serial-in, Serial-out
Serial-in, Parallel-out
Parallel-in, Serial-out
Parallel-in, Parallel-out
Quad Register
Parallel-in, Parallel-out (no shift)
D3 D2 D1 D0
D Q D Q D Q D Q
A B C D
C C C C
CLR CLR CLR CLR
CK
CLR_L
PRESET_L
Q3 Q2 Q1 Q0
Serial-In, Serial-Out
RIN D Q D Q D Q D Q QD
A B C D
C C C C
CLR CLR CLR CLR
CK
CLR_L
PRESET_L
Serial-In, Parallel-Out
RIN D Q D Q D Q D Q
A B C D
C C C C
CLR CLR CLR CLR
CK
CLR_L
PRESET_L
Q3 Q2 Q1 Q0
Parallel-In, Serial-out
D3 D2 D1 D0
RIN
I0 I1 I0 I1 I0 I1 I0 I1
L/S
D Q D Q D Q D Q QD
A B C D
C C C C
CLR CLR CLR CLR
CK
CLR_L
PRESET_L
Universal Shift Register
A B C D
LIN
RIN
S1 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0
S0
D Q D Q D Q D Q
A B C D
C C C C
CLR CLR CLR CLR
CK
CLR_L
PRESET_L
QA QB QC QD
