CD40192BMS

CD40193BMS
CMOS Presettable Up/Down Counters
December 1992 (Dual Clock With Reset)

Features Description
• CD40192BMS - BCD Type CD40192BMS Presettable BCD Up/Down Counter and the
• CD40193BMS - Binary Type CD40193BMS Presettable Binary Up/Down Counter each con-
sist of 4 synchronously clocked, gated “D” type flip-flops con-
• High Voltage Type (20V Rating) nected as a counter. The inputs consist of 4 individual jam lines,
• Individual Clock Lines for Counting Up or Counting a PRESET ENABLE control, individual CLOCK UP and
Down CLOCK DOWN signals and a master RESET. Four buffered Q
signal outputs as well as CARRY and BORROW outputs for
• Synchronous High-Speed Carry and Borrow Propaga-
multiple-stage counting schemes are provided.
tion Delays for Cascading
• Asynchronous Reset and Preset Capability The counter is cleared so that all outputs are in a low state by a
high on the RESET line. A RESET is accomplished asynchro-
• Medium Speed Operation nously with the clock. Each output is individually programmable
- fCL = 8MHz (typ.) at 10V asynchronously with the clock to the level on the corresponding
• 5V, 10V and 15V Parametric Ratings jam input when the PRESET ENABLE control is low.
• Standardize Symmetrical Output Characteristics The counter counts up one count on the positive clock edge of
• 100% Tested for Quiescent Current at 20V the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on the positive clock edge
• Maximum Input Current of 1µA at 18V Over Full Pack- of the CLOCK DOWN signal provided the CLOCK UP line is
age Temperature Range; 100nA at 18V and +25oC high.
• Noise Margin (Over Full Package/Temperature Range)
The CARRY and BORROW signals are high when the counter
- 1V at VDD = 5V is counting up or down. The CARRY signal goes low one-half
- 2V at VDD = 10V clock cycle after the counter reaches its maximum count in the
- 2.5V at VDD = 15V count-up mode. The BORROW signal goes low one-half clock
cycle after the counter reaches its minimum count in the count-
• Meets All Requirements of JEDEC Tentative Standard
down mode. Cascading of multiple packages is easily accom-
No. 13B, “Standard Specifications for Description of
plished without the need for additional external circuitry by tying
‘B’ Series CMOS Devices”
the BORROW and CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the succeeding counter
Applications package.
• Up/Down Difference Counting The CD40192BMS and CD40193BMS are supplied in these
• Multistage Ripple Counting 16-lead outline packages:
• Synchronous Frequency Dividers Braze Seal DIP *H4W, †H4X
• A/D and D/A Conversion Frit Seal DIP H1F
Ceramic Flatpack *H6P, †H6W
• Programmable Binary or BCD Counting * CD40192B Only †CD40193B Only

Pinout Functional Diagram

CD40192BMS, CD40193BMS PRESET
TOP VIEW ENABLE 11

J2 1 16 VDD 15 3 Q1
J1
1 2
Q2 2 15 J1 J2 Q2
10 6
Q1 3 14 RESET J3 Q3
9 7
CLOCK DOWN 4 13 BORROW J4 Q4
5 13
CLOCK UP 5 12 CARRY CLOCK UP BORROW
4 12
CLOCK DOWN CARRY
Q3 6 11 PRESET ENABLE

Q4 7 10 J3 14
RESET VDD = 16
VSS 8 9 J4 VSS = 8

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3363
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1419
 Specifications CD40192BMS, CD40193BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125oC
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20V 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20V 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 Specifications CD40192BMS, CD40193BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS

Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns
Clock Up or Clock Down TPLH1
10, 11 +125oC, -55oC - 675 ns
to Q

Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns
Reset to Q
10, 11 +125oC, -55oC - 675 ns

Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
PE to Q TPLH3 o o
10, 11 +125 C, -55 C - 540 ns

Propagation Delay TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 320 ns
Clock Up to Carry, Clock TPLH4
10, 11 +125oC, -55oC - 432 ns
Down to Borrow

Propagation Delay TPHL5 VDD = 5V, VIN = VDD or GND 9 +25oC - 600 ns
PE to Borrow or Carry TPLH5
10, 11 +125oC, -55oC - 810 ns
o
Propagation Delay TPHL6 VDD = 5V, VIN = VDD or GND 9 +25 C - 600 ns
Reset to Borrow or Carry TPLH6
10, 11 +125oC, -55oC - 810 ns

Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns

Maximum Clock Input FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz
Frequency
10, 11 +125oC, -55oC 1.48 - MHz

NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA

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 Specifications CD40192BMS, CD40193BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 7 - V
-55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 240 ns
Clock Up or Down to Q TPLH1
VDD = 15V 1, 2, 3 +25oC - 180 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 240 ns
Reset to Q
VDD = 15V 1, 2, 3 +25oC - 180 ns
Propagation Delay TPHL3 VDD = 10V 1, 2, 3 +25oC - 200 ns
PE to Q TPLH3
VDD = 15V 1, 2, 3 +25oC - 140 ns
Propagation Delay TPHL4 VDD = 10V 1, 2, 3 +25oC - 160 ns
Clock Up to Carry, Clock TPLH4
VDD = 15V 1, 2, 3 +25oC - 120 ns
Down to Borrow
Propagation Delay TPHL5 VDD = 10V 1, 2, 3 +25oC - 300 ns
PE to Borrow or Carry TPLH5
VDD = 15V 1, 2, 3 +25oC - 220 ns
Propagation Delay TPHL6 VDD = 10V 1, 2, 3 +25oC - 300 ns
Reset to Borrow or Carry TPLH6
VDD = 15V 1, 2, 3 +25oC - 220 ns
Transition Time TTHL1 VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH1
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Rise and TRCL VDD = 5V 1, 2, 3, 4 +25oC - 15 µs
Fall Time TFCL
VDD = 10V 1, 2, 3, 4 +25oC - 15 µs
VDD = 15V 1, 2, 3, 4 +25oC - 5 µs
Minimum Removal Time TREM VDD = 5V 1, 2, 3, 5 +25oC - 80 ns
Reset or PE
VDD = 10V 1, 2, 3, 5 +25oC - 40 ns
VDD = 15V 1, 2, 3, 5 +25oC - 30 ns
Minimum Pulse Width TW VDD = 5V 1, 2, 3 +25oC - 480 ns
Reset
VDD = 10V 1, 2, 3 +25oC - 300 ns
VDD = 15V 1, 2, 3 +25oC - 260 ns
Minimum Pulse Width PE TW VDD = 5V 1, 2, 3 +25oC - 240 ns
VDD = 10V 1, 2, 3 +25oC - 170 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns

7-1422
 Specifications CD40192BMS, CD40193BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 180 ns
Width
VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Input Capacitance CIN Reset 1, 2 +25oC - 15 pF
Input Capacitance CIN All Other Inputs 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
5. The time required for RESET or PRESET ENABLE control to be removed before clocking. See timing diagram defining TREM.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

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 Specifications CD40192BMS, CD40193BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER CD40192BMS, CD40193BMS
Static Burn-In 1 2, 3, 6, 7, 12, 13 1, 4, 5, 8 - 11, 14, 16
(Note 1) 15
Static Burn-In 2 2, 3, 6, 7, 12, 13 8 1, 4, 5, 9 - 11,
(Note 1) 14 - 16
Dynamic Burn- - 8, 14 1, 5, 9 - 11, 15, 16 2, 3, 6, 7, 12, 13 4 -
In (Note 1)
Irradiation 2, 3, 6, 7, 12, 13 8 1, 4, 5, 9 - 11,
(Note 2) 14 - 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

7-1424
 CD40192BMS, CD40193BMS

Logic Diagrams
*RESET
14

*PE
11
S1
*J1 R1 S2 S3 S4
15 R2 R3 R4
** ** **
1 10 9

*J2 *J3 *J4

CONTROL LOGIC 1
**SAME AS CONTROL LOGIC 1

CARRY
12

*CLOCK UP S1 S2 S3 S4

5 S S S S
Q1 Q2 Q3 Q4
CL CL CL CL
Q1 Q2 Q3 Q4
4 R R R R

*CLOCK DOWN R1 R2 R3 R4

13

BORROW

VDD

3 2 6 7
Q1 Q2 Q3 Q4

*ALL INPUTS PROTECTED BY

COS/MOS PROTECTION NETWORK
VSS

FIGURE 1. CD40192BMS LOGIC DIAGRAM (BCD)

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 CD40192BMS, CD40193BMS

Logic Diagrams (Continued)

*RESET
14

*PE
11
S1
*J1 R1 S2 S3 S4
15 R2 R3 R4
** ** **
1 10 9

*J2 *J3 *J4

CONTROL LOGIC 1
**SAME AS CONTROL LOGIC 1

VSS

CARRY
VDD
12

*CLOCK UP S1 S2 S3 S4

5 S S S S
Q1 Q2 Q3 Q4
CL CL CL CL
Q1 Q2 Q3 Q4
4 R R R R

*CLOCK DOWN R1 R2 R3 R4

13

BORROW
VDD VDD

VDD

3 2 6 7
Q1 Q2 Q3 Q4

*ALL INPUTS PROTECTED BY

COS/MOS PROTECTION NETWORK
VSS

FIGURE 2. CD40193BMS LOGIC DIAGRAM (BINARY)

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 CD40192BMS, CD40193BMS

CL

CL CL
CL
CL S
R
p
p Q
S R
Q S n
CL = n
CL CL
Q
R CL
CL
p p

n n
Q

CL CL

FIGURE 3. INTERNAL LOGIC OF FLIP-FLOP

TRUTH TABLE

CLOCK UP CLOCK DOWN PRESET ENABLE RESET ACTION

1 1 0 Count Up
1 1 0 No Count
1 1 0 Count Down
1 1 0 No Count
X X 0 0 Preset
X X X 1 Reset
1 = High Level 0 = Low Level X = Don’t Care

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 5. MIMIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

7-1427
 CD40192BMS, CD40193BMS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC -15 -10 -5 0
OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0
AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

15.0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

12.5 -5

10.0

10V -10V
7.5 -10

5.0
-15V
2.5 -15
5V

0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

400

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
350
TRANSITION TIME (tTHL, tTLH) (ns)

300
200 SUPPLY VOLTAGE (VDD) = 5V
250
SUPPLY VOLTAGE (VDD) = 5V
150 200

150
100 10V
10V
100
15V
50 15V
50

0
0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
LOAD CAPACITANCE FUNCTION OF LOAD CAPACITANCE
106 AMBIENT TEMPERATURE (TA) = +25oC
8
POWER DISSIPATION PER GATE (PD) (µW)

6 CL = 50pF
4
2 CL = 15pF

105 8
6
4

104 8
6
4
2

103
8
6
4
2
102
2 4 68 2 4 6 8 2 4 68 2 4 68 2 4 68
1 10 102 103 104 105
INPUT FREQUENCY (fIN) (kHz)

FIGURE 10. DYNAMIC POWER DISSIPATION

7-1428
 CD40192BMS, CD40193BMS

1
RESET 0 1
RESET 0
PE 1 1
0 PE 0
J1 1
1 J1 0
0
J2 1
1 J2 0
0
J3 1
1 J3 0
0
J4 1
1 J4 0
0
CLK CLK 1
UP 1 UP 0
0
CLK CLK 1
DN 1 DN 0
0
1
Q1 1 Q1 0
0
1
Q2 1 Q2 0
0
1
Q3 1 Q3 0
0
1
1 Q4 0
Q4
0
1
1 CARRY 0
CARRY 0
1
1 BORROW 0
BORROW 0
COUNT 0 13 14 15 0 1 2 1 0 15 14 13
COUNT 0 7 8 9 0 1 2 1 0 9 8 7

FIGURE 11. CD40192BMS TIMING DIAGRAM FIGURE 12. CD40193BMS TIMING DIAGRAM

tWH tWL

CLOCK

RESET
PRESET ENABLE
trem*

*RESET OR PRESET ENABLE

REMOVAL TIME

FIGURE 13. TIMING DIAGRAM DEFINING trem

J1 J2 J3 J4 J1 J2 J3 J4
CARRY CLOCK UP
CLOCK UP CARRY
CD40192BMS CD40192BMS
OR OR
CD40193BMS BORROW CLOCK DOWN CD40193BMS
CLOCK DOWN BORROW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RESET
PRESET
ENABLE

FIGURE 14. CASCADED COUNTER PACKAGES

7-1429
 CD40192BMS, CD40193BMS

Chip Dimensions and Pad Layout

Dimensions and pad layout for the CD40192BMSH

(dimensions and pad layout for the CD40193BMSH
are identical).

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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