CD4518BMS,

CD4520BMS
December
1992 CMOS Dual Up Counters

Features Pinout
• High Voltage Types (20V Rating) CD4518BMS, CD4520BMS
• CD4518BMS Dual BCD Up Counter TOP VIEW

• CD4520BMS Dual Binary Up Counter

• Medium Speed Operation CLOCK A 1 16 VDD
- 6MHz Typical Clock Frequency at 10V ENABLE A 2 15 RESET B
• Positive or Negative Edge Triggering Q1A 3 14 Q4B

• Synchronous Internal Carry Propagation Q2A 4 13 Q3B

Q3A 5 12 Q2B
• 100% Tested for Quiescent Current at 20V
Q4A 6 11 Q1B
• 5V, 10V and 15V Parametric Ratings RESET A 7 10 ENABLE B
• Maximum Input Current of 1A at 18V Over Full Pack- VSS 8 9 CLOCK B
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’ *CD4518B Only Functional
Series CMOS Devices”
†CD4520B Only
Diagram
Applications
• Multistage Synchronous Counting
• Multistage Ripple Counting
CLOCK A
• Frequency Dividers 1
ENABLE A
C
2
Description
CD4518BMS Dual BCD Up Counter and CD4520BMS
Dual Binary Up Counter each consist of two RESET A
identical, internally synchronous 4-stage counters. 7

The counter stages are D-type flip-flops having

interchangeable CLOCK and ENABLE lines for
incrementing on either the positive-going or
negative-going transition. For single unit operation CLOCK B
9
the ENABLE input is maintained high and the
ENABLE B
counter advances on each positive-going transition C
10
of the CLOCK. The counters are cleared by high
levels on their RESET lines.
The counter can be cascaded in the ripple mode by RESET B
connect- ing Q4 to the enable input of the 15
subsequent counter while the CLOCK input of the
latter is held low.
The CD4518BMS and CD4520BMS are supplied in
these 16-lead outline packages:
Braze Seal DIP H4S
Frit Seal DIP H1F
Ceramic Flatpack *H6P †H6W
7-1
 6 13
Q4A R Q3B
14
R Q4B

3
Q1A
4
11 10/
Q1B
Q2A 16
12 10/ VSS = 8
5 Q2B 16
Q3A VDD = 16

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling
Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3342

7-2
 Specifications CD4518BMS, CD4520BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD)............................V to Thermal Resistance . . . . . . . . . . . . . . . . ja
+20V jc Ceramic DIP
(Voltage Referenced to VSS Terminals) and FRIT Package . . . . . 80oC/W
Input Voltage Range, All Inputs.......................V to VDD 20oC/W Flatpack
+0.5V Package . . . . . . . . . . . . . . . . 70oC/W
DC Input Current, Any One Input                        20oC/W
10mA Operating Temperature Range...... . -55oC to Maximum Package Power Dissipation (PD) at +125oC
+125oC For TA = -55oC to +100oC (Package Type D, F, K)...500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) Derate
Storage Temperature Range (TSTG)........... . -65oC to Linearity at 12mW/oC to 200mW
+150oC Device Dissipation per Output Transistor...................100mW
Lead Temperature (During Soldering) For TA = Full Package Temperature Range (All Package
................................................................................... Types) Junction Temperature
+265oC ...................................................................................
+175oC
At Distance 1/16  1/32 Inch (1.59mm  0.79mm) from
case for 10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 A
2 +125oC - 1000 A
o A
VDD = 18V, VIN = VDD or GND 3 -55 C - 10
Input Leakage IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
Current +125oC
2 -1000 - nA
VDD = 3 -55oC -100 - nA
18V
Input Leakage IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
Current +125 C o
2 - 1000 nA
VDD = 3 -55oC - 100 nA
18V
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, - - 50 mV
55oC
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25 C, +125oC, -
o
14.95 - V
55oC
Output Current IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
(Sink)
Output Current IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
(Sink)
Output Current IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
(Sink)
Output Current IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
(Source)
Output Current IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
(Source)
Output Current IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
(Source)
Output Current IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
(Source)
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1 +25oC -2.8 -0.7 V
VSS = 0V, IDD = 10A o
P Threshold Voltage VPTH 1 +25 C 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH VOL V
VDD = 20V, VIN = VDD or GND 7 +25oC > <
VDD/ VDD/
VDD = 18V, VIN = VDD or GND 8A +125oC 2 2
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 1, 2, 3 +25oC, +125oC, - - 1.5 V
(Note 2) 0.5V 55oC
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 1, 2, 3 +25oC, +125oC, - 3.5 - V
(Note 2) 0.5V 55oC
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, - - 4 V
(Note 2) VOL < 1.5V 55oC

7-3
 Specifications CD4518BMS, CD4520BMS
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, - 11 - V
(Note 2) VOL < 1.5V 55oC
NOTES: 1. All voltages referenced to device GND, 100% testing 3. For accuracy, voltage is measured differentially to
being implemented. VDD. Limit is 0.050V max.
2. Go/No Go test with limits applied to inputs.

7-4
 Specifications CD4518BMS, CD4520BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation TPHL1 VDD = 5V, VIN = VDD or 9 +25oC - 560 ns
Delay Clock to TPLH1 GND 10, 11 +125oC, -55oC - 756 ns
Output
Propagation TPHL2 VDD = 5V, VIN = VDD or 9 +25oC - 650 ns
Delay Reset to GND 10, 11 +125oC, -55oC - 878 ns
Ouput
Transition TTHL VDD = 5V, VIN = VDD or 9 +25oC - 200 ns
Time (Note 2) TTLH GND 10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input FCL VDD = 5V, VIN = VDD or 9 +25oC 1.5 - MHz
Frequency GND 10, 11 +125oC, -55oC 1.11 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or 1, 2 -55oC, +25oC - 5 A
GND +125oC - 150 A
VDD = 10V, VIN = VDD or 1, 2 -55oC, +25oC - 10 A
GND +125oC - 300 A
VDD = 15V, VIN = VDD or 1, 2 -55oC, +25oC - 10 A
GND +125oC - 600 A
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, - 50 mV
+125oC,
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, - 50 mV
+125oC,
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, 4.95 - V
+125oC,
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, 9.95 - V
+125oC,
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
(Source) -55oC - -0.64 mA
Output Current IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
(Source) -55oC - -2.0 mA
Output Current IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
(Source) -55oC - -1.6 mA
Output Current IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
(Source) -55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL 1, 2 +25oC, - 3 V
< 1V +125oC,
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL 1, 2 +25oC, +7 - V
< 1V +125oC,
-55oC

7-5
 Specifications CD4518BMS, CD4520BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation TPHL1 VDD = 10V 1, 2, 3 +25oC - 230 ns
Delay Clock to TPLH1 VDD = 15V 1, 2, 3 +25oC - 160 ns
Output
Propagation TPHL2 VDD = 10V 1, 2, 3 +25oC - 225 ns
Delay Reset to VDD = 15V 1, 2, 3 +25oC - 170 ns
Output
Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input FCL VDD = 10V 1, 2, 3 +25oC 3 - MHz
Frequency VDD = 15V 1, 2, 3 +25oC 4 - MHz
Maximum Clock Rise TRCL VDD = 5V 1, 2, 3, 4 +25oC - 15 s
and Fall Time TFCL VDD = 10V 1, 2, 3, 4 +25oC - 5 s
VDD = 15V 1, 2, 3, 4 +25oC - 5 s
Minimum Enable Pulse TW VDD = 5V 1, 2, 3 +25oC - 400 ns
Width VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns
Minimum Reset Pulse TW VDD = 5V 1, 2, 3 +25oC - 250 ns
Width VDD = 10V 1, 2, 3 +25oC - 110 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Minimum Clock Pulse TW VDD = 5V 1, 2, 3 +25oC - 200 ns
Width VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 70 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters
are characterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the
fixed propagation delay of the output of the driving stage for the estimated capacitive load.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or 1, 4 +25oC - 25 A
GND
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage VTN VDD = 10V, ISS = -10A 1, 4 +25oC - 1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage VTP VSS = 0V, IDD = 10A 1, 4 +25oC - 1 V
Delta
Functional F VDD = 18V, VIN = VDD or 1 +25oC VOH VOL V
GND > <
VDD = 3V, VIN = VDD or VDD/ VDD/
GND 2 2
Propagation Delay TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
Time TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 4. Read and Record
20ns.

7-6
 Specifications CD4518BMS, CD4520BMS

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD  1.0A
Output Current (Sink) IOL5  20% x Pre-Test Reading
Output Current (Source) IOH5A  20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V  -0.5V 50kHz 25kHz

Static Burn-In 3-6, 11-14 1, 2, 7-10, 15 16
1
Note 1
Static Burn-In 3-6, 11-14 8 1, 2, 7, 9, 10,
2 15, 16
Note 1
Dynamic - 7, 8, 15 2, 10, 16 3-6, 11-14 1, 9
Burn- In
Note 1
Irradiation 3-6, 11-14 8 1, 2, 7, 9, 10,
Note 2 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
2. Each pin except VDD and GND will have a series resistor of 47K  5%; Group E, Subgroup 2, sample size is 4
dice/wafer, 0 failures, VDD = 10V  0.5V

7-7
 CD4518BMS, CD4520BMS

Logic Diagrams
VDD
Q1 Q2 Q3 Q4
3/11 4/12 5/13 6/14

VSS
* ALL INPUTS ARE PROTECTED D Q D Q D Q D Q
BY CMOS PROTECTION C Q C Q C Q C Q
NETWORK
R R R R
RESET
*
7/15

ENABLE
*
2/10
CLOCK
*
1/9

FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS

VDD
Q1 Q2 Q3 Q4
3/11 4/12 5/13 6/14

VSS
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION D Q D Q D Q D Q
NETWORK
C Q C Q C Q C Q
R R R R
RESET
*
7/15

ENABLE
*
2/10
CLOCK
*
1/9

FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS

TRUTH TABLE
CLOCK ENABLE RESET ACTION
1 0 Increment Counter
0 0 Increment Counter
X 0 No Change
X 0 No Change
0 0 No Change
1 0 No Change
X X 1 Q1 thru Q4 = 0
X = Don’t Care 1  High State 0  Low State

7-8
 CD4518BMS, CD4520BMS
Typical Performance Curves

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V
10 5.0

5 2.5
5V 5V

0 5 10 15
0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-10 - -15 0 -15 -10 - 0
5 0 5 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -

5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -
5V
-10 -5

-15
-10V
-20 -10V -10

-25
-15V
-30 -15V -15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
CHARACTERISTICS
350
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

350
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
PROPAGATION DELAY TIME (tPHL, tPLH)

300 300
SUPPLY VOLTAGE (VDD) = 5V SUPPLY VOLTAGE (VDD) = 5V
250 250

200 200

150 10V 150 10V

100 100
15V
15V
50 50
(ns)

0
0
10 20 30 40 50 60 70 80 90 100
10 20 30 40 50 60 70 80 90 100 110
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY vs LOAD FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPAC- ITANCE, CLOCK OR ENABLE TO CAPACITANCE, RESET TO OUTPUT
OUTPUT

7-9
 CD4518BMS, CD4520BMS

Typical Performance Curves

MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz)

AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) =
+25oC LOAD CAPACITANCE (CL) =
TRANSITION TIME (tTHL, tTLH) (ns)

15
50PF

200

SUPPLY VOLTAGE (VDD) = 10

150 5V

100
10V 5
15V
50

0
0 20 0 5 10 15 20
40 60 80 100
LOAD CAPACITANCE (CL) (pF) SUPPLY VOLTAGE (VDD) (V)

FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY vs
SUPPLY VOLTAGE
POWER DISSIPATION /CONVERTER (PD) (W)

104 8
6
4 SUPPLY VOLTAGE (VDD) = 15V
2

103 8
6
4
2

102 8 10V
6 10V
4
5V
2
CL = 50pF
10 8
6 CL = 15pF
4
2
1 AMBIENT TEMPERATURE (TA) = +25oC
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
0.1 1 10 102 103 104
FREQUENCY (f) (kHz)

FIGURE 11. TYPICAL POWER DISSIPATION CHARACTERISTICS

Timing Diagrams

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CLOCK
ENABLE
RESET
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Q1
Q2
CD4518BMS
Q3
Q4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
Q1
Q2
CD4520BMS
Q3
Q4

FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS

7-10
 CD4518BMS, CD4520BMS

CLOCK
INPUT

VDD
1 2 7 9 10 15 1 2 7 9 10 15

CLOCK ENABLE RESET CLOCK ENABLE RESET CLOCK ENABLE RESET CLOCK ENABLE RESET
A A A B B B A A A B B B

Q1A Q2A Q3A Q4A Q1B Q2B Q3B Q4B Q1A Q2A Q3A Q4A Q1B Q2B Q3B Q4B

3 4 5 6 11 12 13 14 3 4 5 6 11 12 13 14

CD4518BMS/20BMS CD4518BMS/20BMS

FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING

CD4071 CD4071
CLOCK*
INPUT

1 2 3 9 10 15 1 2 3 9 10 15

CLOCK ENABLE RESET CLOCK ENABLE RESET CLOCK ENABLE RESET CLOCK ENABLE RESET
A A A B B B A A A B B B

Q1A Q2A Q3A Q4A Q1B Q2B Q3B Q4B Q1A Q2A Q3A Q4A Q1B Q2B Q3B Q4B
3 4 5 6 11 12 13 14 3 4 5 6 11 12 13 14

CD4520BMS CD4520BMS

CD4012A CD4012A CD4012A

CD4520BMS

* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed
propagation delay at 15pF and the transition time of the output driver stage for the estimated capacitive load.
FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING

7-11
 CD4518BMS, CD4520BMS

Chip Dimensions and Pad Layouts

CD4518BMS CD4520BMS
Dimensions in parenthesis are in millimeters
and are derived from the basic inch
dimensions as indicated. Grid graduations are
in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ  14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems
certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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TEL: (32) 2.724.2111
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 CD4518BMS, CD4520BMS
ASIA
Intersil
(Taiwan
) Ltd.
Taiwan
Limited
7F-6, No. 101
Fu Hsing North
Road Taipei,
Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

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