CO224 – 2020 July
COMPUTER ARCHITECTURE
Introduction
ISURU NAWINNE
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 1
Course Staff
Lecturers:
• Dr. Isuru Nawinne, Dr. Swarnalatha Radhakrishnan
Instructors:
• Mr. Kisaru Liyanage
• Ms. Udaree Kanewela
• Mr. Mahendra Bandara
• Mr. Amila Indika
• Casual Instructors (Buddhi, Rusiru and Shirly)
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 2
Course Structure
Timetable
Mon Wed Fri
8.55am - 9.50am Tutorial/Lab/Discussion
Lecture Lab/Discussion
10.10am - 11.05am
Marks Distribution:
Mid-semester exam 20%
Final exam 40%
Practicals 40%
Syllabus & Course Plan…
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 3
Before we begin…
• Labs will be marked in the class.
No submissions.
• Plagiarism will not be tolerated
• Work hard and self-study
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 4
Labs & Tutorials
• Will be announced in advance, on FEeLS:
https://feels.pdn.ac.lk/course/view.php?id=721
• Usual routine each practical:
Introductory tutorial on Wednesday 8.55 - 9.50 a.m.
Lab session(s) on following Wednesday(s) 8.55 - 11.05 a.m.
** You must spend extra time before the lab session to complete
• Topics 1-4 : ARM Assembly Programming
Topics 5-6 : Building a processor system using Verilog HDL
• 100% participation required for labs & tutorials
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 5
Labs & Tutorials
• Work in groups of two (your choice)
• Lab Rooms
• Marks for labs:
• Complete and demonstrate the work in the class itself,
marks given out of 100 for the group
• Every lab topic will have a 10-20 minutes quiz at the end,
individually marked, out of 1
• Your marks = group marks × individual + group marks
(1st 50%) quiz marks (2nd 50%)
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 6
Lab Groups
• Find a partner
• Put your names & reg. numbers in the Google sheet
(do this today itself, access to lab rooms will be based on this)
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 7
Architecture: The Big-Picture
Algorithm
Write h.264
Programming Language
C
Source Code
Compile / Link
Compiler / Linker Work on Micro architecture
gcc
Binary Image
processor
Collection of assembly instructions Micro-Architecture
AMD
Implement Athlon
Target Instruction Set
Micro arc
based on Intel
Intel x86 x86
Logic Gates
Using Logic gates , transistors … Micro architecture is built to Transistors
support target instruction set.
Silicon
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 8
Architecture: The Big-Picture
Algorithm
Write h.264
Programming Language
C
Source Code
Compile / Link
Compiler / Linker
ARM gcc
Binary Image
We cannot use std gcc , coz of ARM v8
target instruction set
Micro-Architecture
Qualcomm
Implement Kryo
Target Instruction Set
based on ARM
v8
ARM v8
Logic Gates
Transistors
Silicon
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 9
Cross Compiler and Emulator
qemu
(emulator)
arm-gcc
(cross-compiler) We haven’t physical processor to run compiled code.
For that we use emulator. (It can emulate ARM insructions)
Cross-Compiler : Compiled code run on other processor
How to use these tools?
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 10
Lab 0 – Background
Self-study exercise:
• What are RISC & CISC architectures?
• What are the differences and uses of RISC/CISC?
• Compare ARM, Atmel AVR and Intel x86 architectures
Google and Wikipedia are your friends but keep in mind to
verify the sources of online information!
Tutorial 1 – Introduction to Assembly (Wednesday 9-11 am)
ISURU NAWINNE CE - FACULTY OF ENGINEERING - UOP 11
