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CG2027 - Assign - 1 - Solution

The document is an assignment solution for a digital circuits course. It contains the solutions to two problems: 1) Calculating timing parameters like rise time, fall time, and propagation delays for a CMOS inverter based on a given waveform. The rise time is found to be 23.92 ps, fall time 19.01 ps, and propagation delays 12.26 ps and 13.30 ps. 2) Calculating noise margin high and low for an inverter chain. The noise margin high is 0.10 V and noise margin low is 0.15 V. If the input high and low of the second buffer are the same, it would maximize the noise margins.

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297 views2 pages

CG2027 - Assign - 1 - Solution

The document is an assignment solution for a digital circuits course. It contains the solutions to two problems: 1) Calculating timing parameters like rise time, fall time, and propagation delays for a CMOS inverter based on a given waveform. The rise time is found to be 23.92 ps, fall time 19.01 ps, and propagation delays 12.26 ps and 13.30 ps. 2) Calculating noise margin high and low for an inverter chain. The noise margin high is 0.10 V and noise margin low is 0.15 V. If the input high and low of the second buffer are the same, it would maximize the noise margins.

Uploaded by

Peng Fei
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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National University of Singapore

Electrical and Computer Engineering

CG2027 (Transistor-Level Digital Circuits)


Assignment #1 Solution
AY21/22 Semester 1
Issued: Aug. 10, 2021 Due: Aug. 15, 2021 (18:00)

Problem 1: Delay Calculation

The objective of this problem is to figure out correct delay / risetime / falltime of a CMOS inverter, based on
the information given from the waveform.

123.08ps 350.43ps

108.62ps 355.05ps

101.80ps 362.06ps

113.35ps 383.86ps

120.88ps 368.35ps

132.36ps 359.95ps

250 500

a) What is the rise time (tr), fall time (tf) of the output waveform Vout?

➔ tr =383.86-359.95 = 23.92 (ps), tf =132.36 –113.35 = 19.01 (ps)

b) What is the high-to-low propagation delay (tpHL) of the logic? ➔ tpHL =120.88 – 108.62= 12.26 (ps)

c) What is the low-to-high propagation delay (tpLH) of the logic? ➔ tpLH = 368.35 – 355.05= 13.30 (ps)

d) If the given waveform is the half of the clock cycle with 50% duty, what is the clock frequency?

➔ You can choose any half-clock cycle points. E.g., 350.43-101.80 = 248.63ps (half cycle), 2 ×248.63ps
≈ 0.5ns (1 cycle). Therefore, the clock freq is approx. 2GHz (note: ±5% difference is allowed)
Problem 2: Noise Margin

Buf Buf
1 2

Buf2 input high: > 0.75V


Buf1 output high: 0.85 – 1.0V Buf2 input low: <0.25V
Buf1 output low: 0 – 0.10V

a) For the inverter chain given above, calculate the noise margin high (NMH) and noise margin low (NML).

➔ NMH= |VOH1– VIH2| = |0.85 – 0.75| = 0.10 (V)

➔ NML = |VOL1– VIL2| = |0.10 – 0.25| = 0.15 (V)

b) What happens if input high and input low of the Buf2 become the same? Explain.

➔ Noise margin high and noise margin low will be maximized.

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