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EE210 Assignment5 Solution

This document is an assignment cover page for EE 210: Digital Logic Systems at Alfaisal University. It provides instructions for submitting Assignment #5, which is due on April 21, 2021 at 11:59pm. The assignment contains 2 problems related to digital logic design using gates and blocks. Problem 1 asks students to show the characteristic equation for the complement output of a T flip-flop. Problem 2 asks students to design a sequential circuit with two JK flip-flops that can count up or down based on the values of two inputs.

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194 views4 pages

EE210 Assignment5 Solution

This document is an assignment cover page for EE 210: Digital Logic Systems at Alfaisal University. It provides instructions for submitting Assignment #5, which is due on April 21, 2021 at 11:59pm. The assignment contains 2 problems related to digital logic design using gates and blocks. Problem 1 asks students to show the characteristic equation for the complement output of a T flip-flop. Problem 2 asks students to design a sequential circuit with two JK flip-flops that can count up or down based on the values of two inputs.

Uploaded by

sarah alsh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Alfaisal University - College of Engineering

Electrical Engineering Department


EE 210: Digital Logic Systems
Assignment #5
Spring 2021 - Due Date: April 21, 2021 at 11:59pm (midnight)

Student Name: SOLUTION

Student Number:

I declare that this submission is my own, and that no part of it has been copied from another source except
where properly acknowledged.
Student’s signature: _________________________

Follow the guidelines below in submitting your work.


1. Your homework should have this cover page duly filled out by you.
2. Where possible and applicable, your solution should be typed and printed.
3. Use white, preferably plain, A4-sized paper in your submission.
4. Start a new page for every new problem. However, more than one sub-problem (or short
problems) can be answered on the same sheet.
5. Arrange problems in the order they are assigned. Do not change problem numbers.
6. Show your work in an organized manner. Do not crowd your solution pages.
7. Elaborate on any assumptions made or shortcuts (jumps) taken in your solution.
8. Reference your figures, tables, constants, equations and conversions, used to complete the
problem.

Problem P1 P2 Total
Mark
Maximum 10 40 50

Evaluator’s initials: _______________


Date: _______________

Course Learning Outcomes (CLO) Problems

Design digital logic systems using gates and blocks (de/multiplexers,


CLO1 2
encoders/decoders, adders, latches, flip lops, registers, etc.)
Alfaisal University - College of Engineering
Electrical Engineering Department
EE 210: Digital Logic Systems
Assignment #5
Spring 2021 - Due Date: April 21, 2021 at 11:59pm (midnight)

Problem 1:
Show that the characteristic equation for the complement output of a T flip-flop is

Answer:
For T – Flip-Flop

Q (t + 1) = TQ′ + T′Q = T ⊕ Q
Q′ (t + 1) = [T ⊕ Q]′
= T′Q′ + TQ

Another answer:

Problems 2:
Design a sequential circuit with two JK flip-flops A and B, and two inputs E and F.

The circuit operates as follows.


 If E =0, the circuit remains in the same state regardless of the value of F.
 When E = 1 and F = 1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back
to 00, and repeats.
 When E = 1 and F = 0, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back
to 00, and repeats.
Alfaisal University - College of Engineering
Electrical Engineering Department
EE 210: Digital Logic Systems
Assignment #5
Spring 2021 - Due Date: April 21, 2021 at 11:59pm (midnight)

Answer:

Binary up-down counter with enable E.


Alfaisal University - College of Engineering
Electrical Engineering Department
EE 210: Digital Logic Systems
Assignment #5
Spring 2021 - Due Date: April 21, 2021 at 11:59pm (midnight)

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